Via Technologies, Inc.

Yao-Chun Su

Jui-Ming Wei

Cheng-Wei Huang

Ruei-Ling Lin

Wei-Hsiang Hong

Chih-Kuo Kao

Peter Chia

I Lin Hsieh

A computer system has a central processing unit, a north bridge electrically connected to the central processing unit, memory electrically connected to the north bridge, a south bridge electrically connected to the north bridge, and a peripheral device electrically connected to the south bridge. The south bridge includes a register for storings a plurality of pre-fetched read data to provide the pre-fetched read data to the peripheral device. The north bridge has an address queue module for storing an address of the pre-fetched read data, and a snooping module for checking whether a data value corresponding to the address is updated by the CPU. The north bridge assists the south bridge in obtaining and maintaining the pre-fetched read data for high efficiency and accuracy of read caching of the south bridge.

Apparatus and related method for maintaining read caching data of south bridge with north bridge

A request scheduling method is provided in a request accessing system having a processing unit, an upstream unit coupled to the processing unit, a downstream unit coupled to the processing unit and the upstream unit, and at least one endpoint device coupled to the upstream unit and the downstream unit, wherein the endpoint device asserts at least one request to the upstream unit. The request scheduling method includes: transmitting the request to a processing unit while the request is a non-peer-to-peer request, and transmitting the request to a downstream unit while the request is a peer-to-peer request; wherein if the request is a peer-to-peer and posted request and there is a previous asserted request which is peer-to-peer and non-posted request and the previous asserted request has a latency exceeds a predetermined time, transmitting the request earlier than the previous asserted request to the downstream unit.

Method and system for request accessing and scheduling

A chip for use with both a high-speed bus and a low-speed bus in a computer system includes a test control unit recorded therein a preset address data for determining a transmission path of an external signal in a test mode of the chip; an upstream control unit for transmitting the external signal to the high-speed bus in a normal operation mode of the chip, coupled to the test control unit for optionally receiving the external signal in the test mode; and a downstream control unit for transmitting the external signal to the low-speed bus in the normal operation mode of the chip, coupled to the test control unit for optionally receiving the external signal in the test mode.

Chip for use with both high-speed bus and low-speed bus and operation method thereof

The present invention provides a method for receiving an instruction for varying the bus frequency from a current bus frequency to a new frequency. The method may include storing a group of parameters corresponding to a second frequency, disabling a link connected to the host bus at a first frequency while the host bus is being operated with parameters corresponding to the first frequency, updating the parameters for operating the host bus with the group of parameters, and enabling the link at the second bus frequency to operate the host bus with the group of parameters.

Methods and systems for varying bus frequencies

A method for a power management of a central processor unit is disclosed. The method is applied to when the central processor unit is in a low power state without snooping and a bus master signal is sent from a peripheral device. First, a South Bridge sends a control signal to a central processor unit to drive the central processor unit to enter a low power state allowing snooping. Afterward an arbiter of the North Bridge is enabled. If the bus master signal is sent from the peripheral device to the South Bridge, an arbiter of the South Bridge is also enabled. And then the bus master signal is snooped by the central processor unit and the data is transmitted. After the bus master signal is snooped and the data has been transmitted, the arbiters are disabled and the South Bridge drives the central processor unit to return to the low power state without snooping.

Method for power management of central processor unit

A connected indicator wire of open-drained configuration is set between a north bridge and a south bridge. When either the south or north bridge is handling a bus master request, a bus master indicator (BMI) signal is asserted to the connected indicator wire. With open-drained configuration, the signal of the connected indicator wire is capable of reflecting whether a BMI signal is asserted, and accordingly, the south bridge controls the CPU to switch between power saving states for responding to the bus master request. The CPU does not have to resume a full-function power state to coordinate a bus master service.

Apparatus and related method of coordinating north bridge and south bridge for processing bus master requests of peripheral devices for controlling a central processing unit to operate in a power-saving state

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Taipei, Taiwan

Yao-Chun Su