Taiwan Semiconductor Manufacturing Comp. Ltd.

Yao-Ching Ku

Ru-Gun Liu

Chih-Ming Lai

Tsong-Hua Ou

Ying-Chou Cheng

Wen-Chun Huang

Cliff Hou

Boren Luo

Tsai-Sheng Gau

Kuei Shun Chen

I-Chang Shin

Min-Hong Wu

Chin-Hsiang Lin

Anthony Yen

Yi-Kan Cheng

Hsiao-Shu Chao

Te-Chih Huang

Chih-Yang Yeh

George Liu

Yu-Po Tang

Wen-Hao Liu

Yu Lun Liu

Shu-Chen Lu

Hsin-Chang Lee

Chun-Kuang Chen

Yun-Yue Lin

Hung-Chang Hsieh

Chih-Cheng Lin

Hsien-Cheng Wang

Ming-Chang Wen

Yung-Chin Hou

Wei-Jen Lo

Chung-Kai Lin

Yih-Yuh Doong

Hsuan-Chen Chen

Ping-Heng Yeh

Mark Chien

Lee-Chung Lu

Shinn-Sheng Yu

Ming-Feng Shieh

Burn Jeng Lin

Hua-Tai Lin

Chih-Ming Ke

Sheng-Chi Chin

Chia-Chu Liu

I-Hsiung Huang

Heng-Jen Lee

Vencent Chang

Ming-Che Wu

Chien Wen Lai

Norman Chen

Cherng-Shyan Tsay

Chia-Chi Lin

Chien-Hsun Lin

Louis Chao-Chiuan Liu

Cheng Cheng Kuo

Ken Wu

Luke Hsu

Hung-Ting Pan

Grace H Ho

Shih-Ying Chen

Chen Kun Tsai

Chi-Lin Lu

Wen Chun Huang

Li-Heng Chou

Jung Ting Chen

A method for fabricating a pellicle includes forming a first dielectric layer over a back surface of a substrate. After forming the first dielectric layer, and in some embodiments, a graphene layer is formed over a front surface of the substrate. In some examples, after forming the graphene layer, the first dielectric layer is patterned to form an opening in the first dielectric layer that exposes a portion of the back surface of the substrate. Thereafter, while using the patterned first dielectric layer as a mask, an etching process may be performed to the back surface of the substrate to form a pellicle having a pellicle membrane that includes the graphene layer.

Pellicle fabrication methods and structures thereof

A partially fabricated semiconductor device includes a semiconductor overlay structure. The semiconductor overlay structure includes a first gate stack structure over the semiconductor substrate, the first gate stack structure being configured as an overlay mark in an overlay region of the semiconductor substrate. The semiconductor overlay structure further includes a doped region in the semiconductor substrate surrounding the first gate stack structure. The doped region has a first dopant concentration greater than or equal to a second dopant concentration next to a second gate stack structure in a device region of the semiconductor substrate.

Structure and method for overlay marks

The overlay mark and method for making the same are described. In one embodiment, a semiconductor overlay structure includes gate stack structures formed on the semiconductor substrate and configured as an overlay mark, and a doped semiconductor substrate disposed on both sides of the gate stack structure that includes at least as much dopant as the semiconductor substrate adjacent to the gate stack structure in a device region. The doped semiconductor substrate is formed by at least three ion implantation steps.

An embodiment of a feed-forward method of determining a photomask pattern is provided. The method includes providing design data associated with an integrated circuit device. A thickness of a coating layer to be used in fabricating the integrated circuit device is predicted based on the design data. This prediction is used to generate a gradating pattern. A photomask is formed having the gradating pattern.

Method of defining an intensity selective exposure photomask

The present disclosure provides one embodiment of a method for an integrated circuit (IC). The method includes forming a mandrel pattern on a substrate by a first lithography process; forming a first spacer pattern on sidewalls of the mandrel pattern; removing the mandrel pattern; forming a second spacer pattern on sidewalls of the first spacer pattern; removing the first spacer pattern; and etching the substrate using the second spacer pattern as an etch mask.

Integrated circuit layout and method with double patterning

An intensity selective exposure photomask, also describes as a gradated photomask, is provided. The photomask includes a first region including a first array of sub-resolution features. The first region blocks a first percentage of the incident radiation. The photomask also includes a second region including a second array of sub-resolution features. The second region blocks a second percentage of the incident radiation different that the first percentage. Each of the features of the first and second array includes an opening disposed in an area of attenuating material.

Intensity selective exposure photomask

A method and system for fabricating a substrate is disclosed. First, a plurality of process chambers are provided, at least one of the plurality of process chambers adapted to receive at least one plasma filtering plate and at least one of the plurality of process chambers containing a plasma filtering plate library. A plasma filtering plate is selected and removed from the plasma filtering plate library. Then, the plasma filtering plate is inserted into at least one of the plurality of process chambers adapted to receive at least one plasma filtering plate. Subsequently, an etching process is performed in the substrate.

Method to improve mask critical dimension uniformity (CDU)

An intensity selective exposure photomask, also describes as a gradated photomask, is provided. The photomask includes a first region including a first array of sub-resolution features. The first region blocks a first percentage of the incident radiation. The photomask also includes a second region including a second array of sub-resolution features. The second region blocks a second percentage of the incident radiation different that the first percentage.

A method of designing an integrated circuit ('IC') is provided that includes placing an IC design, where the IC design includes a first element, a second element, and a path coupling the first and second elements, and routing the IC design. Further, the method includes obtaining at least one of resistivity data and capacitance data related to the path, and obtaining timing data related to the path. The method also includes using at least one of the resistivity data, the capacitance data, and the timing data to determine a critical dimension ('CD') bias to be applied to the path, and modifying the IC design, where modifying includes applying the CD bias to the path.

Driven metal critical dimension  (CD) biasing

Methods and systems for providing processing parameters in a secure format are disclosed. In one aspect, a method for providing semiconductor fabrication processing parameters to a design facility is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a model from the set of processing parameters; converting the model into a corresponding set of kernels; converting the set of kernels into a corresponding set of matrices; and communicating the set of matrices to the design facility. In another aspect, a method for providing semiconductor fabrication processing parameters is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a processing model from the set of processing parameters; encrypting the processing model into a format for use with a plurality of EDA tools; and communicating the encrypted processing model format to a design facility.

Model import for electronic design automation

Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data.

Table-based DFM for accurate post-layout analysis

An integrated circuit (IC) design method includes providing an IC layout contour based on an IC design layout of an IC device and IC manufacturing data; generating an effective rectangle layout to represent the IC layout contour; and simulating the IC device using the effective rectangular layout.

Method for shape and timing equivalent dimension extraction

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Hsinchu, Taiwan

Yao-Ching Ku