Realtek Semiconductor Inc.

National Yang Ming Chiao Tung University

Yao-Chia Liu

Bo-Yu Chen

Wei-Zen Chen

Yuan-Sheng Lee

Chi-Kung Kuan

An-Ming Lee

Yu-Ping Huang

Chi-Wei Yen

Zheng-Hao Hong

Chia-Tse Hung

Tung-hsien Tsai

A decision feedback equalizer includes an adder, a comparison device, a register, and a decision feedback coefficient (DFC) generator. The comparison device includes N data comparator(s), each of which includes a feedback compensation circuit, an input-stage circuit, a gain-stage circuit, and a latch in sequence. The feedback compensation circuit determines a degree of compensation according to feedback coefficients from the DFC generator and feedback compensation bits from the N data comparator(s), so that the input-stage circuit, the gain-stage circuit, and the latch can process an analog input signal from the adder according to the degree of compensation and thereby output a data comparison result to the register. The DFC generator determines the feedback coefficients according to the data comparison result.

Decision feedback equalizer

A phase rotation control method includes: detecting whether a phase of an output clock signal of a phase interpolator is going to be switched from a current quadrant to a next quadrant according to a trigger signal to generate a state signal; determining a phase adjustment direction of the output clock signal according to an original phase control signal and the state signal to generate a update signal and first control signals; generating the trigger signal and a selection signal according to the update signal and generating second control signals according to the state signal and the first control signals; and when the phase of the output clock signal is switched to the next quadrant, outputting the second control signal as a phase control signal according to the selection signal, in which the phase interpolator adjusts the phase of the output clock signal according to the phase control signal.

Phase rotation controller and phase rotation control method

A quadrant alternate switching phase interpolator includes first and second multiplexer circuits, a phase interpolator circuitry, and a controller circuitry. The first multiplexer circuit outputs one of first and second clock signals to be a first signal in response to first and third bits in a quadrant control code. The second multiplexer circuit outputs one of third and fourth clock signals to be a second signal in response to second and fourth bits in the quadrant control code, and the first, the third, the second, and fourth clock signals are sequentially different in phase by 90 degrees. The phase interpolator circuitry generates an output clock signal in response to the first and the second signals and phase control bits. The controller circuitry performs a bit-shift operation on the phase control bits to adjust a phase of the output clock signal.

Quadrant alternate switching phase interpolator and phase adjustment method

A phase interpolator includes phase interpolator circuitries. The phase interpolator circuitries generate an output clock signal from an output node according to phase control bits and clock signals. Phases of the clock signals are different from each other. Each phase circuitry includes phase buffer circuits. Each phase buffer circuit is turned on according a first bit and a second bit of the phase control bits, in order to generate a signal component in the output clock signal according to a corresponding clock signal of the clock signals. Each phase buffer circuit includes a first resistor and a second resistor, and transmits one of a first voltage and a second voltage to the output node according to the corresponding clock signal, in which the first voltage is transmitted to the output node via the first resistor, and the second voltage is transmitted to the output node via the second resistor.

Phase interpolator and phase buffer circuit

The present invention discloses a transceiver apparatus having phase-tracking mechanism. A phase detection circuit of a receiver circuit performs sampling and phase detection on an input data signal according to a sampling clock signal to generate a phase detection result. A proportional gain circuit of the receiver circuit applies a proportional gain operation on the phase detection result to generate a phase adjusting signal. A CDR circuit of the receiver circuit receives a source clock signal to generate the sampling clock signal and performs phase-adjusting according to the phase adjusting signal. The integral gain circuit apples an integral gain operation on the phase detection result to generate a frequency adjusting signal. The source clock generating circuit receives a reference clock signal to generate the source clock signal and perform frequency-adjusting according to the frequency adjusting signal. The transmitter circuit performs signal transmission according to the source clock signal.

Transceiver apparatus and transceiver apparatus operation method thereof having phase-tracking mechanism

A signal equalizer comprising: a feedback system, configured to acquire at least one signal value of an edge region of an input signal, and configured to adjust the signal value according to a crossing part of an eye diagram such that the crossing part converges to a zero point, wherein the crossing part corresponds to the edge region.

Signal equalizer and signal equalizing method

The present disclosure provides a clock data recovery apparatus. The clock data recovery apparatus includes a phase detection circuit, a digital filter, a phase-interpolating circuit and an oscillator circuit. The phase detection circuit receives and samples a data signal according to multiple reference clock signals having different phases, to generate a phase detection result. The digital filter performs accumulation on the phase detection result, to generate a phase-adjusting signal. The phase interpolator circuit performs phase adjustment on a source clock signal according to the phase-adjusting signal, in order to generate an injection clock signal. The oscillator circuit generates the reference clock signals according to the injection clock signal, in which the phases of the reference clock signals follow the phase of the injection clock signal.

Clock data recovery apparatus and clock data recovery method

An equalizer circuit includes a first arithmetic circuit, a second arithmetic circuit, a data sampling circuit, and an edge sampling circuit. The first arithmetic circuit is configured to compensate an equalization sequence by secondary feedback sequences to output a first added sequence. The second arithmetic circuit is configured to compensate the first added sequence by a primary feedback sequence to output a second added sequence. The data sampling circuit samples, according to data clock, the second added sequence to output a primary sequence, and gains the primary sequence to output the primary feedback sequence. The data sampling circuit sequentially samples, according to the data clock, the primary sequence to output secondary sequences. The data sampling circuit gains the corresponding secondary sequences to output the secondary feedback sequences. The edge sampling circuit is configured to sequentially sample, according to an edge clock, the first added sequence to output an edge sequence.

Equalizer circuit

A clock data recovery circuit includes: a first detecting circuit for detecting phases of an incoming data signal and a sampling clock signal to generate a first detection signal; a loop filter for generating a control signal according to the first detection signal; a second detecting circuit for detecting phases of a reference signal and a feedback signal to generate a second detection signal; a control voltage generating circuit for generating a control voltage based on the second detection signal; a voltage-controlled oscillator for generating the sampling clock signal according to the control voltage; a phase adjustment circuit for adjusting the phase of the sampling clock signal according to the control signal to generate the phase-adjusted signal; and a frequency divider circuit for conducting a frequency division operation on the phase-adjusted signal to generate the feedback signal.

Clock data recovery circuit

A timing control device and a timing control method for a high frequency signal system, the timing control method respectively control trigger points of reset signals, and process the controlled reset signals and clock signals to obtain a signal group with having an absolute timing relationship.

Timing control device and method for high frequency signal system

A multi-level pulse-amplitude modulation receiver system includes an analog equalizer, a digital equalizer, an automatic level tracking engine and an automatic gain controller. The analog equalizer and the automatic gain controller perform signal compensation on a multi-bit quasi-attenuation signal to generate a multi-level compensation signal. The digital equalizer receives the multi-level compensation signal, the positive threshold voltage and the negative threshold voltage, and thereby converts the multi-level compensation signal into a plurality of digital data. The automatic level tracking engine uses the digital data to generate a positive threshold voltage, a negative threshold voltage, at least two positive DC level voltages, and at least two negative DC level voltages, and the positive threshold voltage is an average of the two positive DC level voltages to avoid the nonlinear effect of the analog front end.

Multi-level pulse-amplitude modulation receiver system

A low voltage quadrature phase wideband relaxation oscillator. An ultra-wideband tuning range from Mega to Giga Hz order is also realized by tuning the I/Q coupling factor, zeros and poles. Preferably, a novel synchronous quadrature injection lock is proposed to validate low noise performance.

Growing community of inventors

Hsinchu, Taiwan

Yao-Chia Liu