Macronix International Co., Ltd.

Yao-An Chung

Yuan-Chieh Chiu

Kuang-Chao Chen

Shih-Ping Hong

Kuang-Wen Liu

Ting-Feng Liao

A method for fabricating a memory device includes: providing a substrate; forming a first dielectric layer over the substrate; forming a plurality of conductive layers and a plurality of dielectric layers alternately and horizontally disposed on the substrate; forming a channel column structure on the substrate and in the plurality of conductive layers and the plurality of dielectric layers, where a side wall of the channel column structure is in contact with the plurality of conductive layers; forming a second dielectric layer covering the first dielectric layer; and forming, in the first and second dielectric layers, a conductive column structure adjacent to the channel column structure and in contact with one of the plurality of conductive layers, where the conductive column structure includes a liner insulating layer as a shell layer.

Method for fabricating memory device

A memory device includes a substrate. A first dielectric layer is disposed over the substrate. A plurality of conductive layers and a plurality of dielectric layers are alternately and horizontally disposed on the substrate. A channel column structure is disposed on the substrate and in the conductive layers and the dielectric layers. A side wall of the channel column structure is in contact with the plurality of conductive layers. A second dielectric layer covers the first dielectric layer. A conductive column structure is in the first and second dielectric layers, adjacent to the channel column structure, and in contact with one of the plurality of conductive layers. The conductive column structure includes a liner insulating layer as a shell layer.

Memory device and method for fabricating the same

A semiconductor structure for three-dimensional memory device and a manufacturing method thereof are provided. In the manufacturing method, clean plasma is used to clean the impurity doped regions, formed by slit etching, in the surface layer of the substrate to decrease the contact resistance between substrate and conductive plugs formed in the slits. The bottom part of the conductive plugs each has a reduced neck structure and an enlarged bottom structure.

Semiconductor structure for three-dimensional memory device and manufacturing method thereof

Provided is a memory device including a plurality of bit line layers and a plurality of supporting structures. Each bit line layer extends in a plane defined by a first direction and a second direction and has a plurality of bit lines extending along the first direction. Each bit line has a plurality of wide parts and a plurality of narrow parts arranged alternately. The supporting structures are disposed between the wide parts of the corresponding bit lines of adjacent bit line layers. Besides, each narrow part of each bit line substantially has an ellipse-like shape in cross section, and each narrow part has a rounding ratio (RR) of greater than about 30%.

Memory device and method of forming the same

Provided is a memory device including a plurality of first conductive line layers, a plurality of support structures, and a charge storage layer. Each of the first conductive line layers extends along a plane defined by a first direction and a second direction. Each of the first conductive line layers includes a plurality of first conductive lines extending along the first direction. The support structures are located between the adjacent first conductive line layers. The charge storage layer covers upper surfaces, lower surfaces, and two side surfaces of the first conductive lines and surfaces of the support structures.

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Hsin-Chu, Taiwan

Yao-An Chung