Hefechip Corporation Limited

Yanzun Li

John H Zhang

Huang Liu

Devendra K Sadana

Liang Li

Guoliang Zhu

Chunyu Wong

Haijiang Yuan

Chung-Chiang Lin

Yuan Lung Lin

Tongqing Chen

Brian Li Ji

A semiconductor structure and a method of forming it are disclosed by the present application. Deep trench capacitors are formed in a substrate, and fin contacts formed by upper portions of inner electrodes in the deep trench capacitors are connected to fins on a surface of the substrate. At least one of word lines formed on the substrate pass over and are separated by a word line isolation layer from the inner electrodes. The word line isolation layer covers portions of the inner electrodes between a buried oxide layer and the fin contacts, while the fins are exposed therefrom.

Semiconductor structure and forming method thereof

A semiconductor structure includes a substrate having a doped silicon substrate, a buried oxide layer, and a silicon device layer. A capacitor having an inner electrode and a node dielectric layer is formed in the substrate. The inner electrode and the node dielectric layer extend into the doped silicon substrate. A select transistor is disposed in the silicon device layer. An embedded contact is disposed atop the capacitor to electrically couple a doped region of the select transistor with the inner electrode. A first dielectric layer is disposed around the select transistor. A second dielectric layer is deposited on the first dielectric layer. A contact plug is formed in the second dielectric layer and the first dielectric layer and is in direct contact with the embedded contact. A memory stack with a MTJ element is disposed on the contact plug.

Semiconductor structure and fabrication method thereof

A semiconductor device for a volatile memory is disclosed. The semiconductor device includes a substrate, a side wall and an epitaxial liner. The substrate has a first height and is made of a first material having a first lattice parameter. The side wall defines a deep trench. The epitaxial liner is disposed around the side wall, is made of a second material having a second lattice parameter, and has a second height having a same level with the first height, wherein the epitaxial liner and the side wall cooperate for creating a desired aspect ratio for the deep trench.

Semiconductor device for a volatile memory and method of manufacturing semiconductor device

A semiconductor device including a silicon-on-insulator (SOI) wafer comprising a doped silicon substrate, a buried oxide layer on the doped silicon substrate, and a silicon device layer on the buried oxide layer. An inner electrode and a node dielectric layer of a capacitor are disposed in a trench of the SOI wafer. The inner electrode and the node dielectric layer penetrate through the buried oxide layer and extend into the doped silicon substrate. At least a select transistor is disposed on the buried oxide layer. The select transistor includes a source doping region and a drain doping region, a channel region between the source doping region and the drain doping region, and a gate over the channel region. At least an embedded contact is disposed atop the capacitor to electrically couple the drain doping region of the select transistor with the inner electrode of the capacitor.

Semiconductor device and fabrication method thereof

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Lagrangeville, NY, United States of America

Yanzun Li