Altera Corporation

Intel Corporation

Microsoft Technology Licensing, LLC

Cypress Semiconductor Corporation

Yanzhong Xu

Jeffrey T Watt

Irfan Rahim

Jun Liu

Weimin Zhang

Nelson Joseph Gaspard

Andy Louie Lee

Albert Ratnakumar

Qi Xiang

Srinivas Perisetty

Shankar Sinha

Lin-Shih Liu

Shih-Lin S Lee

Jeffrey Xiaoqi Tung

Wen Wu

Mark Chan

Christopher J Pass

Che Ta Hsu

Dale Ibbotson

Tracey DellaRova

David Lewis

Bonnie I Wang

Kyung Suk Oh

Haiming Yu

Oliver Pohland

Teng Chow Ooi

Guang Chen

Charu Sardana

Nor Razman Md Zin

Nelson Jospeh Gaspard

The present disclosure includes storage circuits, such latches. In one embodiment, a circuit includes a plurality of latches, each latch including a first N-type transistor formed in a first P-type material, a first P-type transistor formed in a first N-type material, a second N-type transistor formed in a second P-type material, and a second P-type transistor formed in a second N-type material. The first and second N-type transistors are formed in different P-wells and the first and second P-type transistors are formed in different N-wells. In other storage circuits, charge extraction transistors are coupled to data storage nodes and are biased in a nonconductive state. These techniques make the data storage circuits more resilient, for example, to an ionizing particle striking the circuit and generating charge carriers that would otherwise change the state of the storage node.

Resilient storage circuits

A circuit may include a ring oscillator circuit and monitoring circuitry. The ring oscillator circuit has a group of inverters in a loop, whereby the group of inverters includes first, second, and third output nodes. The monitoring circuitry may monitor for error events in a signal that has passed through the inverters from any one of the first, second, or third output nodes, and may generate first and second monitoring circuitry outputs. The circuit may further include an error correction circuit that produces an error correction output based on the first and second monitoring circuitry outputs. Accordingly, the monitoring circuitry may generate first and second updated monitoring circuitry outputs based on the error correction output. The first and second updated monitoring circuitry outputs may be logically combined using a logic circuit to reset the signal that has passed through the loop.

Techniques for detecting and correcting errors on a ring oscillator

An integrated circuit is provided that includes memory elements that exhibit immunity to soft error upset (SEU) events when subjected to high-energy atomic particle strikes. Each memory element may include at least two inverting circuits coupled in a feedback loop. Transistors in the memory element may be grouped in one contiguous region or divided into multiple separate regions. The memory element may include a long gate conductor that extends outside the boundary of the one contiguous region or the multiple separated regions. The long gate conductor may serve to provide parasitic resistance in the feedback loop to help mitigate SEU disturbances.

Memory elements with soft-error-upset (SEU) immunity using parasitic components

An integrated circuit that includes an array of random-access memory cells is provided. Each memory cell may include inverting circuits formed from pull-up transistors and pull-down transistors and also access transistors coupled to the inverting circuits. The pull-up transistors may be formed in an n-well. The memory cells may also be coupled to single event latch-up (SEL) prevention circuitry. The SEL prevention circuitry may include a clamping circuit, a voltage sensing circuit, and a driver circuit. In response to a single event alpha particle strike at one of the memory cells, a temporary voltage rise may be presented at the clamping circuit. The voltage sensing circuit may detect the voltage rise and direct the driver circuit to bias the n-well into deep reverse bias region. Operated in this way, the SEL prevention circuitry can mitigate SEL while minimizing memory cell leakage.

Memory with single-event latchup prevention circuitry

An on-die-capacitor structure includes a first capacitor and a second capacitor. The first capacitor may have first and second terminals. The first and second terminals are directly connected to first and second power supply rail structures, respectively. The first power supply rail structure is different from the second power supply rail structure. The second capacitor may have third and fourth terminals. The second capacitor is connected in series between the second power supply rail structure and a third power supply rail structure. The third power supply rail structure is different from the first and second power supply rail structures. The third and fourth terminals are directly connected to the second and third power supply rail structures, respectively. The first capacitor may have a first capacitance and the second capacitor structure may have a second capacitance that is greater than the first capacitance.

On-die capacitor (ODC) structure

Integrated circuits having flip-flops with asynchronous reset capabilities are provided. The flip-flops may be single event upset (SEU) hardened registers implemented using dual-interlocked cell (DICE) latch circuits. A logic gate may be inserted at the data input of each flip-flop. A multiplexer may be inserted at the input of the clock tree that is being used to feed clock signals to each of the flip-flops. Both the logic gate and the multiplexer may receive an asynchronous reset signal. The multiplexer may also receive a normal clock signal and a delayed clock pulse signal that is triggered in response to detecting assertion of the reset signal.

Register circuitry with asynchronous system reset

An integrated circuit may have an array of memory elements. Each memory element may have multiple memory cells. Each memory element may have a voting circuit that receives signals from the memory cells in that memory element. The voting circuit can produce an output based on the signals. The signals stored by the memory cells of each memory element may be redundant so that the voting circuit can produce an accurate output even in the event that a radiation strike causes some of the memory cells to flip their states to erroneous values. The memory elements may be based on memory cells such as static random-access memory cells and thyristor-based cells.

Memory array with redundant bits and memory element voting circuits

A method and apparatus for reducing global interconnect delay on a field programmable gate array (FPGA) on an integrated circuit die comprising coding with a digital to analog coder on the integrated circuit die successive groups of n digital bits into an 2level voltage or current signal where n is an integer greater than or equal to 2; transmitting the voltage or current signal on a global interconnect on the integrated circuit die; receiving on the integrated circuit die the signal transmitted on the global interconnect; and decoding the received signal on the integrated circuit die to reconstitute the successive groups of digital bits.

CMOS global interconnect using multi-voltage(or current)-levels

Illustratively, a finFET comprises at least one fin, and typically several fins, with a trapping region in or on a substrate at the base of each fin to trap ions produced by radiation incident on the substrate. In one embodiment, the trapping region is an implanted region having a conductivity type opposite that of the substrate. In another, the trapping region is a defect region. In another, the trapping region is an epitaxial region grown on the substrate. The finFET is formed by forming the fin or fins and then forming the trapping region at the base of the fin. Illustratively, the trapping region is formed by implanting in the substrate ions having a conductivity type opposite that of the substrate or by creating defects in the substrate or by epitaxially growing a region or regions having an opposite conductivity type to that of the substrate.

FinFET with improved SEU performance

Integrated circuits with memory elements are provided. An integrated circuit may include logic circuitry formed in a first portion having complementary metal-oxide-semiconductor (CMOS) devices and may include at least a portion of the memory elements and associated memory circuitry formed in a second portion having nano-electromechanical (NEM) relay devices. The NEM and CMOS devices may be interconnected through vias in a dielectric stack. Devices in the first and second portions may receive respective power supply voltages. In one suitable arrangement, the memory elements may include two relay switches that provide nonvolatile storage characteristics and soft error upset (SEU) immunity. In another suitable arrangement, the memory elements may include first and second cross-coupled inverting circuits. The first inverting circuit may include relay switches, whereas the second inverting circuit includes only CMOS transistors. Memory elements configured in this way may be used to provide volatile storage characteristics and SEU immunity.

Memory elements with relay devices

Circuitry may include a substrate with an input and an output circuit coupled in series at an intermediate node. The output circuit may have an output transistor and a stack transistor coupled in series between an output node and a voltage supply terminal. The two circuits may be placed on the substrate such that a single event transient charge injected into a sensitive diffusion of the intermediate node is shared through the substrate with the sensitive diffusion of the stack transistor of the output circuit. The charge sharing may reduce the recovery time at the output node and help to reduce the recovery time at the intermediate node, thereby providing increased single event transient robustness and reducing the probability of a permanent flip of the intermediate node and the output node of the circuitry.

Optimal stacked transistor placement to increase single event transient robustness

An illustrative finFET comprises first, second, and third pluralities of fins having gate structures and source and drain regions formed on the fins so that first PMOS transistors are formed in first epitaxial regions on the first plurality of fins, NMOS transistors are formed in second epitaxial regions on the second plurality of fins and second PMOS transistors are formed in third epitaxial regions on the third plurality of fins. In three embodiments, the fins are formed in silicon; the first epitaxial region is silicon germanium; the second region is silicon; and the third region is 1) silicon, 2) silicon carbide, or 3) silicon or silicon carbide on a silicon carbide cladding. In another embodiment, the third epitaxial regions are wide band gap semiconductors formed on wide band gap semiconductor fins. In another embodiment, all the fins and epitaxial regions are wide band gap semiconductors.

Low leakage FinFET

Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.

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Santa Clara, CA, United States of America

Yanzhong Xu