Huawei Technologies Co., Limited

Yanxiang Liu

Xiaolong Ma

Wen Yang

Yu Xia

Yue Pan

Stephane Badel

Yongjie Zhou

Xinfang Liu

Miao Xu

Sunhom Steve Paak

Daxiang Wang

Zanfeng Chen

Huabin Chen

A field-effect transistor structure includes a semiconductor substrate, a metal gate, a metal trench for source, a metal trench for drain, an etching-stop layer, and a gate contact. The etching-stop layer is overlaid on the metal trench for source and the metal trench for drain. The gate contact is above an active region.

FinFET structure having a gate contact above a metal gate and straddling the boundary of an active region

A memory and an electronic device are provided. The memory includes a storage element (), a first transistor (), a second transistor (), a first bit line (BLA), and a second bit line (BLB). The storage element () is coupled to the first bit line (BLA) and the second bit line (BLB) by separately using the first transistor () and the second transistor (), and the first transistor () and the second transistor () are turned on during a write operation. When the foregoing solution is used, compared with providing a required write current by using one transistor, providing the write current by using the two transistors may enable a smaller transistor to meet a requirement, thereby reducing an area required by the entire memory. In addition, the memory in this application can still support a dual-port feature in a read operation.

Memory and electronic device

This application provides an integrated circuit device and a preparation method thereof, and relates to the field of semiconductor technologies. An isolation section for suppressing a leakage current path of two adjacent transistors may be formed by using a simple process. The integrated circuit device includes a substrate and a fin protruding from the substrate. The integrated circuit device further includes two adjacent transistors. The two adjacent transistors use two spaced segments on the fin as respective channels of the two adjacent transistors. A part that is of the fin and that is located between the two spaced segments is processed to obtain an isolation section. The isolation section is used to suppress current transfer between the two channels of the two adjacent transistors.

Integrated circuit device and preparation method thereof

A memory includes a transistor and a magnetic tunnel junction (MTJ) storage element, a bottom electrode of the MTJ storage element is electrically connected to a drain electrode of the transistor using a conduction structure, wiring layers are disposed between the transistor and the MTJ storage element in the storage area, and a dielectric layer is filled between adjacent wiring layers, the conduction structure includes a first conduction part, and the first conduction part includes a first metal wire, a second metal wire, and a first via hole, the wiring layers comprise a first wiring layer, a second wiring layer, and a third wiring layer, the first via hole penetrates a dielectric layer and the third wiring layer that are located between the first wiring layer and the second wiring layer.

Memory

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Shenzhen, China

Yanxiang Liu