Qualcomm Incorporated

Intel Corporation

Yanru Li

Dexter Tamio Chun

Jungwon Suh

Jung Pill Kim

Azzedine Touzni

Alain Artieri

Deepti Vijayalakshmi Sriramagiri

Michael Hawjing Lo

Moinul H Khan

Alexander Gantman

Xiangyu Dong

Dhamim Packer Ali

Ali Taha

Nhon Toai Quach

Subrato Kumar De

Chia-Hung Sophia Kuo

Dhaval Kanubhai Patel

Mosaddiq Saifuddin

Jay Yu Jae Choi

Devdutt Patnaik

Sreenivasulu Reddy Chalamcharla

Daison Davis Koola

Eric Taseski

Ruchi Parekh

Bohuslav Rychlik

Thomas Klingenbrunn

Sungryul Kim

Rahul Gulati

Amit Gil

Amin Ansari

Subbarao Palacharla

Terrence Brian Remple

Haw-Jing Lo

George Patsilaras

Andrew Edmund Turner

Richard Alan Stewart

Thomas Zeng

Assaf Shacham

Michael Drop

Vinod Chamarty

Raghu Sankuratri

Javid Jaffari

Alex Tu

Virat Deepak

Kedar Bhole

Erez Tsidon

Pratik Patel

Suryanarayana China Chittuluri

Ashutosh Shrivastava

William Kimberly

Mamta Desai

Jeong-Ho Woo

Larry A Bassel

William Zand

Pavan Kumar Thirunagari

Oscar Cabral Arias

Venkata Narayana Ramesh Pinnamaraju Durga

Dhaval Patel

Embodiments of apparatuses and methods for dynamic prioritization of interconnect traffic in a system-on-chip are described. In an embodiment, an apparatus includes first circuitry to use a first weight value to weight operating system priority information to generate a first weighted priority value, second circuitry to use a second weight value to weight system-on-chip (SoC) hardware priority information to generate a second weighted priority value, third circuitry to sum the first weighted priority value and the second weighted priority value to generate a quality of service (QoS) value for an SoC interconnect transaction, and an arbiter to use the QoS value to prioritize the SoC interconnect transaction on an SoC interconnect.

Dynamic prioritization of system-on-chip interconnect traffic using information from an operating system and hardware

Various embodiments may include methods and systems for providing secure in-memory device access of a memory device by a system-on-a-chip (SOC). Various methods may include receiving a configuration message from the SOC for configuring a memory access control of the memory device, and configuring the memory access control based on the configuration message. Various embodiments may include receiving an access request message from the SOC requesting access to a memory base address and a memory access range of a memory cell array of the memory device, wherein the access request message includes a read/write operation. Various embodiments may include comparing the access request message with the configured memory access control to determine whether the access request message is allowable. Various embodiments may further include performing the read/write operation in response to determining that the access request message is allowable.

Methods and apparatus for in-memory device access control

In a conventional memory subsystem, a memory controller issues explicit refresh commands to a DRAM memory device to maintain integrity of the data stored in the memory device when the memory device is in an auto-refresh mode. A significant amount of power may be consumed to carry out the refresh. To address this and other issues, it is proposed to allow a partial refresh in the auto-refresh mode in which the refreshing operation may be skipped for a subset of the memory cells. Through such selective refresh skipping, the power consumed for auto-refreshes may be reduced. Operating system kernels and memory drivers may be configured to determine areas of memory for which the refreshing operation can be skipped.

Partial refresh technique to save memory refresh power

Transferring data between memories may include reading data associated with a memory transfer transaction from a first memory, determining whether a bypass indication associated with the memory transfer transaction is asserted, and transferring the data from the first memory to a second memory. The transferring may include bypassing the first-processing if the bypass indication is asserted. The transferring may further include bypassing second-processing the data if the bypass indication is asserted. Following bypassing the second-processing, the data may be stored in the second memory.

Protected data streaming between memories

Embodiments of the present disclosure relate to an apparatus, comprising a first memory controller, to receive a signal from a component coupled with the first memory controller, where the signal indicates that data is to bypass a volatile memory device coupled with the first memory controller and be written to a byte-addressable write-in-place persistent memory device coupled with the first memory controller; determine, in response to the received signal, whether a write buffer in a second memory controller, coupled with the first memory controller, is empty; direct, if the write buffer is empty, the data to the write buffer for temporary storage prior to storage in the persistent memory device, to bypass the volatile memory device; and direct, if the write buffer is not empty, the data to the volatile memory device.

Bypassing cache memory in a write transaction in a system with multi-level memory

Various additional and alternative aspects are described herein. In some aspects, the present disclosure provides a method of calibrating a component. The method includes receiving previous calibration parameters for an external component at a secondary SoC from a primary SoC, wherein the secondary SoC is coupled to the external component and configured to calibrate the external component. The method further includes determining validity of the previous calibration parameters by the secondary SoC. The method further includes operating the external component by the secondary SoC based on the determined validity of the previous calibration parameters.

Boot time determination of calibration parameters for a component coupled to a system-on-chip

Systems, methods, and computer programs are disclosed for providing coincident memory bank access. One embodiment is a memory device comprising a first bank, a second bank, a first bank resource, and a second bank resource. The first bank has a first set of bitlines for accessing a first set of rows in a first memory cell array. The second bank has a second set of bitlines for accessing a second set of rows in a second memory cell array. The first bank resource and the second bank resource are selectively connected to the first set of bitlines or the second set of bitlines via a cross-connect switch.

Coincident memory bank access via cross connected shared bank resources

Various additional and alternative aspects are described herein. In some aspects, the present disclosure provides a method of controlling a memory of a computing device by an adaptive memory controller. The method includes collecting usage data from the computing device over a first bin, wherein the first bin is associated with a first weight, wherein the first weight is indicative of one or more of a first partial array self-refresh (PASR) setting a first partial array auto refresh (PAAR) setting and a first deep power down (DPD) setting. The method further includes associating the collected data with a second weight, adapting the first bin based on the second weight, wherein the second weight is indicative of one or more of a second PASR, PAAR, and DPD setting. The method further includes controlling the memory during the next first bin based on the second weight.

Adaptive power management of dynamic random access memory

Systems, methods, and computer programs are disclosed for refreshing a volatile memory. An embodiment of a method comprises storing, in a volatile memory device comprising a cell array having a plurality of rows with a corresponding row address, a table specifying one of a data valid indicator and a data invalid indicator for each of the plurality of row addresses. The data valid indicator specifies that the corresponding row is in use, and the data invalid indicator specifies that the corresponding row is not in use. A memory controller initiates a refresh command. In response to the refresh command, the rows having the data valid indicator are refreshed while the rows having the data invalid indicator are skipped.

Selective volatile memory refresh via memory-side data valid indication

Provided are an apparatus and method to cache data in a first memory that is stored in a second memory. At least one read-with-invalidate command is received to read and invalidate at least one portion of a cache line having modified data. The cache line having modified data is invalidated in response to receipt of read-with-invalidate commands for less than all of the portions of the cache line.

Read-with-invalidate modified data in a cache line in a cache memory

Systems, methods, and computer programs are disclosed for scheduling decompression of an application from flash storage. One embodiment of a system comprises a flash memory device and a preemptive decompression scheduler component. The preemptive decompression scheduler component comprises logic configured to generate and store metadata defining one or more dependent objects associated with the compressed application in response to an application installer component installing a compressed application to the flash memory device. In response to a launch of the compressed application by an application launcher component, the preemptive decompression scheduler component determines from the stored metadata the one or more dependent objects associated with the compressed application to be launched. The preemptive decompression scheduler component preemptively schedules decompression of the one or more dependent objects based on the stored metadata.

Preemptive decompression scheduling for a NAND storage device

In conventional memory systems, no access control is performed when write-x and datacopy0 are issued. To address this issue, it is proposed to provide access control to these commands by leveraging the mechanism to enforce access control to normal write commands so that the mechanism is also applied to the write-x and datacopy0 commands.

Write access control for double data rate write-x/datacopy0 commands

System and methods for booting a system-on-chip (SOC) in an enhanced memory mode are described herein. In one aspect, an enhanced memory mode indicator may be read to create a trusted channel to a non-volatile random-access memory (NVRAM). The NVRAM may be logically connected to the SOC. In an aspect, the NVRAM may be secured prior to the creation of the trusted channel. Once the secure channel to NVRAM has been created, the SOC may operate in an enhanced memory mode. Prior to the SOC powering down, the system may store an indicator operable to enable a subsequent boot of the SOC in the power saving mode. The SOC may be operable to switch between the power saving mode and a normal mode depending on the operational requirements of the portable computing device in which the SOC is implemented.

System and method for booting within a heterogeneous memory environment

Growing community of inventors

San Diego, CA, United States of America

Yanru Li