Apple Inc.

Yanran Yang

Mridul Agarwal

Richard F Russo

Deepankar Duggal

Sandeep Kumar Gupta

Tyler J Huberty

Kulin N Kothari

Douglas C Holman

Debasish Chandra

Eric Jason Furbish

Peter G Soderquist

Vivek Venkatraman

Haoyan Jia

Chandan Shantharaj

Stephen G Meier

Sahil Kapoor

Chang Xu

An apparatus includes a cache memory circuit, a prefetcher circuit, and a prefetch deny list circuit, including a plurality of entries, may be included. The cache memory circuit may be configured to store information retrieved from a lower-level memory. The prefetcher circuit may be configured to generate a prefetch request for a particular prefetch address. The prefetch deny list circuit may be configured to allocate, in response to an indication from the cache memory circuit that a previously prefetched address went unused, a given entry, of the plurality of entries, for the previously prefetched address. The prefetch deny list circuit may be further configured to determine whether a particular address for a particular prefetch request corresponds to an active one of the plurality of entries. In response to a determination that a particular active entry corresponds to the particular address, prefetch deny list circuit may deny the particular prefetch request.

Deny list for a memory prefetcher circuit

A livelock resolution circuit may be used to detect and remove a livelock from a processor. The livelock resolution circuit may use a counter, whose value may be reset or incremented depending on a status of a retire pointer in a reorder buffer circuit (ROB). When the retire pointer fails to move from one operation to another over a period of time, the value in the counter may continuously increment to exceed a threshold, indicating that the period of time elapses without a successful retirement of an operation from the ROB. Thus, the livelock resolution circuit may determine that a livelock occurs. To remove the livelock, the livelock resolution circuit may involve a single-step operational mode, where the livelock resolution circuit may demand only one operation (or microoperation) to be executed at each step. As a result, the operation may be retired and the livelock may be removed.

Livelock detection and resolution using oldest operation tracking

A system, e.g., a system on a chip (SOC), may include one or more processors. A processor may execute an instruction synchronization barrier (ISB) instruction to enforce an ordering constraint on instructions. To execute the ISB instruction, the processor may determine whether contexts of the processor required for execution of instructions older than the ISB instruction are consumed for the older instructions. Responsive to determining that the contexts are consumed for the older instructions, the processor may initiate fetching of an instruction younger than the ISB instruction, without waiting for the older instructions to retire.

Processing of synchronization barrier instructions

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Sunnyvale, CA, United States of America

Yanran Yang