Xilinx, Inc.

Yanran Chen

Pierre Maillard

Michael J Hart

Martin L Voogel

Sagheer Ahmad

Ygal Arbel

Krishnan Srinivasan

Jun Liu

Hing Yan To

Sarosh Azad

Edward C Priest

James Murray

Betty Y Lau

Pramod Bhardwaj

Techniques to provide transaction redundancy in an IC include receiving an original memory access request directed to a first memory aperture, constructing a redundant memory access directed to a second memory aperture, and selectively returning a response of the first or second memory aperture to an originator based on contents of the responses. For a write operation, if acknowledgement indicators of the responses indicate success, a response is returned to the originator. For a read operation, if acknowledgement indicators of the responses indicate success and data returned in the response match one another, a response is returned to the originator. If the acknowledgement indicators indicate success, but the data does not match, a retry of the original and redundant read requests is initiated. If any of the acknowledgement indicators do not indicate success, an error is declared. In a mixed-criticality embodiment, the redundant memory access request may be constructed selectively.

Integrated circuit transaction redundancy

One example of the present disclosure is an integrated circuit (IC). The IC includes an inverter with an input and an output, a clock transmission gate coupled to the output of the inverter; and a plurality of storage cells. The clock transmission gate is coupled to each of the plurality of storage cells, wherein each of the plurality of storage cells comprises a plurality of nodes arranged based on a minimum spacing.

Designing single event upset latches

Some examples described herein provide for an on-die virtual probe in an integrated circuit structure for measurement of voltages. In an example, an integrated circuit comprises a voltage-controlled frequency oscillator circuitry and a processor circuitry. The voltage-controlled frequency oscillator circuitry comprises a plurality of circuitry components and is configured to generate a signal having a frequency related to a supply voltage. The voltage-controlled frequency oscillator circuitry is disposed at a location of the integrated circuit proximal to the supply voltage being monitored. The processor circuitry is configured to identify a relationship between the frequency of the signal and the supply voltage. The processor circuitry is also configured to determine a value of the supply voltage associated with the signal based on the identified relationship. The processor circuitry further monitors on-die transient voltages at the location of the integrated circuit based on the value of the supply voltage.

On-die virtual probes (ODVP) for integrated circuitries

An integrated circuit (IC) chip having circuitry adapted to detect and unlatch a latched transistor, and methods for operating the same are provided. In one example, an IC chip includes a body, a power rail disposed in the body and coupled to at least one of a plurality of contact pads disposed on the body, and a first core circuit disposed in the body. The first core circuit includes a first current limiting circuit, a silicon controlled rectifier (SCR) device having a first transistor, a second transistor, and a first latch sensing circuit. The first current limiting circuit is coupled to the power rail. First terminals of the first and second transistors are coupled to the first current limiting circuit. The first latch sensing circuit has a first input terminal coupled to second terminals of the first and second transistors. The first latch sensing circuit also has an output terminal coupled to the first current limiting circuit.

Single event latch-up (SEL) mitigation detect and mitigation

A circuit for storing data in an integrated circuit is described. The circuit comprises an input adapted to receive the data; a memory element coupled to the input, the memory element comprising a storage node for storing the data; at least one node that is separate from the storage node for storing the data; and at least a portion of a dummy transistor coupled to the at least one node that is separate from the storage node for storing the data. A method of storing data in an integrated circuit is also described.

Circuit for and method of storing data in an integrated circuit device

A circuit for storing data in an integrated circuit is described. The circuit comprises an inverter comprising a first transistor having a first gate configured to receive input data and a first output configured to generate a first inverted data output and a second transistor having a second gate configured to receive the input data and a second output configured to generate a second inverted data output; a first pass gate coupled to the first output of the inverter; a second pass gate coupled to the second output of the inverter; and a storage element having an input coupled to receive an output of the first pass gate and an output of the second pass gate. A method of storing data in an integrated circuit is also described.

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San Jose, CA, United States of America

Yanran Chen