Atmel Corporation

Dibcom

Yannick Levy

Khaled Maalej

Emmanuel Hamman

Amaury Demol

Julien Schmitt

Charles-Henri Prat

A wireless signal amplification system including amplification apparatus () consisting of numerous different amplifiers (to) which are distributed in an analogue processing chain (). Also, a converter () for converting analogue signals into digital signals which, at input, are connected to the outlet of the analogue processing chain () and, at output, are connected to at least the gain control circuit () of the amplification apparatus () according to a value that is representative of a characteristic of the wireless signal (). In this way, sampling of the wireless signal () by the converter () is optimized. The gain control circuit () establishes an average gain control signal (), and also has, for each of the amplifiers (to), a device for calculating an individual gain control signal (to) according to a transfer function (Hto H) which is specific to each amplifier and which is applied to the average gain control signal.

Wireless signal amplification system and a television signal decoder comprising one such system

A timing recovery circuit in a QAM demodulator which uses a symbol rate continuously adaptive interpolation filter. The method of interpolation used in the present invention is defined as a function of time per interpolation interval, rather than as a function of time per sampling interval as is commonly implemented in the prior art. This allows the interpolation filtering to be totally independent of the symbol rate in terms of complexity and performance and provides a better rejection of adjacent channels, since the interpolator rejects most of the signal outside the bandwidth of the received channel.

Timing recovery circuit in a QAM demodulator

A quadrature amplitude modulation type demodulator having a dual bit error rate estimator unit that allows for high bit error rate measurements. The dual bit error rate estimator circuit uses information pertaining to the number of corrected bytes from a forward error correction decoder and the count of recognizable patterns of the frame over a sufficiently large number of frames. The two pieces of information can be compared at the bit error rate levels, where both the pattern recognition counter and the FEC decoder are able to output valid data. A comparison between the two pieces of information provides a way to detect the type of noise which occurs on the network and makes it easier to correct problems in signal transmission.

Dual bit error rate estimation in a QAM demodulator

A quadrature amplitude modulation (QAM) type demodulator having a pair of direct digital synthesizer (DDS) circuits. The first DDS circuit is located in a baseband conversion circuit before a receive filter and digitally tunes the signal within the receive filter bandwidth. The second DDS circuit is within a carrier recovery circuit located after the receive filter and serves to fine tune the signal phase.

Direct digital synthesis in a QAM demodulator

A QAM demodulator having a carrier recovery circuit that includes a phase estimation circuit and an additive noise estimation circuit which produces an estimation of the residual phase noise and additive noise viewed by the QAM demodulator. The phase noise estimation is based on the least mean square error between the QAM symbol decided by a symbol decision circuit and the received QAM symbol. The additive noise estimation is based on the same error as in the phase noise estimation, except that it is based only on QAM symbols having the minimum amplitude on the I and Q coordinates. The additive noise estimation is not dependent on the phase of the signal, thus, is independent of the phase noise estimator.

Phase noise and additive noise estimation in a QAM demodulator

A QAM demodulator having a first automatic gain control circuit which outputs a first signal that is a function of the received signal, the first signal being used to control the gain of an amplifier which supplies the input of an A/D converter, and a second automatic gain controller which outputs a second signal derived from the QAM circuit after filtering, the second signal controlling the gain of a digital multiplier which produces a signal which feeds into a equalizer by way of a receive filter. The dual automatic gain control circuits, situated before and after the receive filters, allow for better resistance to non-linearity caused by signals in adjacent channels. Additionally, the dual automatic gain control circuits allow for the amplification level of the signal to be limited before the demodulator to eliminate signal distortion and to be set to the correct level internally with digital gain. Also, there is no saturation of the A/D converter since there is no QAM feedback to analog circuits. This architecture is particularly efficient in a variable rate transmission scheme.

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Paris, France

Yannick Levy