Marvell International Limited

Texas Instruments Corporation

Marvellworld Trade Ltd.

Yanni Chen

Rajesh Juluri

Kedar Shirali

Leilei Song

Konstantinos Sarrigeorgidis

Hongyuan Zhang

Sudhir Srinivasa

Manish Goel

Mao Yu

Yuming Zhu

Sri Varsha Rottela

B Hari Ram

Dale E Hocevar

Lokesh Sundaramurthy Satrasala

Chusong Xiao

Yong Ma

Systems and methods for detecting data in a received multiple-input-multiple-output signal are provided. N signals are received from N respective antennas, where the received signals are associated with (i) M sets of data values, (ii) a set of symbols, and (iii) a set of carrier frequencies. The N signals are formed into a received signal vector y, and one or more transformations are performed on the received signal vector y to obtain a transformed vector. A plurality of samples are formed from the transformed vector. For samples of the plurality of samples, a data detection technique of a plurality of data detection techniques is selected. The selecting is based on at least one of a spatial stream, a symbol, and a carrier frequency associated with the given sample. The selected data detection, technique is used to detect data of the given sample.

Systems and methods for detecting data in a received multiple-input-multiple-output (MIMO) signal

A discrete Fourier transform calculation apparatus includes a plurality of multiplier units, and a plurality of butterfly calculation units. Each butterfly calculation unit is configured to perform simultaneous calculations for at least two stages of a fast Fourier transform (FFT) algorithm by using shared resources of the butterfly calculation unit. Each butterfly calculation unit includes a respective memory device to store input data for the corresponding at least two stages of the FFT algorithm, and a respective butterfly calculator coupled to the respective memory device. Each butterfly calculation unit also includes a respective controller coupled to the respective memory device and the respective butterfly calculator. The respective controller is configured to control the corresponding butterfly calculation unit to calculate the corresponding at least two stages of the FFT algorithm. The plurality of butterfly calculation units and the plurality of multiplier units are coupled in series.

Discrete fourier transform calculation method and apparatus

A high throughput and scalable MIMO detector can use a K-Best detection algorithm to find K combinations of transmit symbols that are likely to be the symbols that were actually transmitted. The K-best MIMO detector can include a plurality of stages, where each stage may correspond to a transmit antenna, and each stage can find K best symbol combinations based on information from a previous stage. To find the new K best symbol combinations, at each stage, a plurality of metrics for potential combinations are computed and sorted by magnitude. The MIMO detector preferably uses a high throughput, merge sorting algorithm to sort the metrics.

Apparatus and method for finding likely combinations of transmitted symbols

Methods and apparatus are provided for performing log-likelihood ratio (LLR) computations in a pipeline. Portions of a metric used to compute LLR values are computed in one pipeline part. The portions correspond to all permutations of some received signal streams. The portions are combined with one permutation xof the received signal stream that was not included in the previous pipeline computation in a subsequent pipeline part to produce M values associated with a particular bit position. At each subsequent clock cycle, a different permutation of xis combined with the previously computed portions producing different M values. State values corresponding to different values of bit positions of the received stream are computed by finding the minimum among the M values, in each clock cycle, that affect a particular bit position. The state values are combined to compute the LLR values for the bit position in a final pipeline part.

Methods and apparatus for providing a maximum likelihood (ML) decoding pipeline for quadruture phase-shift keying (QPSK) multiple-input-multiple-output (MIMO) orthogonal frequency division multiplexing (OFDM) receivers

High-throughput pipelined and scalable architecture for a K-Best MIMO detector

Methods and apparatus for providing a maximum likelihood (ML) decoding pipeline for quadrature phase-shift keying (QPSK) multiple-input-multiple-output (MIMO) orthogonal frequency division multiplexing (OFDM) receivers

Discrete Fourier transform calculation method and apparatus

Methods and apparatus are provided for computing reliability values in a pipeline. A reliability value portion is computed, with control circuitry in a first pipeline stage, based on a difference between a received input signal value and an expected value. The reliability value portion is combined, in a second pipeline stage that follows the first pipeline stage, with a first value derived from the received input signal to generate a first reliability value. A determination is made as to whether to update the first reliability value in a third pipeline stage based on a combination of the first reliability value with a second reliability value that corresponds to a second value derived from the received input signal.

Methods and apparatus for providing a ML decoding pipeline for QPSK MIMO OFDM receivers

Methods and apparatus are provided for performing LLR value computations in a pipeline. Portions of a metric used to compute LLR values are computed in one pipeline part. The portions correspond to all permutations of some received signal streams. The portions are combined with one permutation xof the received signal stream that was not included in the previous pipeline computation in a subsequent pipeline part to produce M values associated with a particular bit position. At each subsequent clock cycle, a different permutation of xis combined with the previously computed portions producing different M values. State values corresponding to different values of bit positions of the received stream are computed by finding the minimum among the M values, in each clock cycle, that affect a particular bit position. The state values are combined to compute the LLR values for the bit position in a final pipeline part.

A method and systems for reducing the complexity of a parity checker are described herein. In at least some preferred embodiments, a parity-check decoder includes column store units and one or more alignment units, which are coupled to the column store units. The column store units outnumber the alignments units.

Parity check decoder architecture

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Sunnyvale, CA, United States of America

Yanni Chen