International Business Machines Corporation

Stmicroelectronics Gmbh

Globalfoundries Inc.

Tokyo Electron Limited

Elpis Technologies Inc.

Lam Research Corporation

Yann Mignot

Hsueh-Chung Chen

Yongan Xu

Chi-Chun Liu

Ekmini Anuja De Silva

Lawrence Alfred Clevenger

Su Chen Fan

Muthumanickam Sankarapandian

James John Kelly

Joe Lee

Junli Wang

Nelson M Felix

Christopher Joseph Waskiewicz

Chanro Park

Hosadurga K Shobha

Cornelius Brown Peethala

Chih-Chao Yang

Eric R Miller

Mary Claire Silvestre

Nicolas J Loubet

Terry Allen Spooner

Pierre Morin

Indira P Seshadri

Stuart A Sieg

Kangguo Cheng

John Christopher Arnold

Peng Xu

Andrew Mark Greene

Koichi Motoyama

Marc Adam Bergendahl

Douglas M Trickett

Choonghyun Lee

Oleg Gluschenkov

Lars W Liebmann

Zhenxing Bi

Ashim Dutta

Gangadhara Raja Muthinti

Kristin Schmidt

Yannick Feurprier

Matthew T Shoudy

Alex Joseph Varghese

Dallas M Lea

Mehmet Yilmaz

Carl John Radens

Theodorus E Standaert

Hemanth Jagannathan

John H Zhang

Terence B Hook

Ruqiang Bao

Fee Li Lie

Injo Ok

Joshua T Smith

Daniel Sanders

Dario Leonardo Goldfarb

Chun Wing Yeung

Cheng Chi

Robert L Bruce

Shyng-Tsong Chen

Yiheng Xu

Wenhui Wang

Robin Hsin Kuo Chao

Praveen Joseph

Richard Stephen Wise

Brown Cornelius Peethala

Luciana Meli Thompson

Sylvie M Mignot

Bassem M Hamieh

Brent A Anderson

Effendi Leobandung

Daniel C Edelstein

Julien Frougier

Son Van Nguyen

Benjamin David Briggs

Wenyu Xu

Soon-Cheon Seo

Christopher J Penny

Oscar Van Der Straten

Xunyuan Zhang

Gauri V Karve

Allen H Gabor

Tao Li

Somnath Ghosh

Jing Guo

Tsung-Sheng Kang

Matthew S Angyal

Dominik Metzler

Ming He

Shariq Siddiqui

Dimitri Houssameddine

Alan C Thomas

Eric Miller

Bhaskar Nagabhirava

Michael Goss

Jim E Kelly

Martha Inez Sanchez

Jennifer A Oakley

Seowoo Nam

Devika Sil

Shanti Pancharatnam

Lijuan Zou

A semiconductor device includes a conductive line disposed within a dielectric layer, a metal layer disposed over and in direct contact with the conductive line, and a metallization layer disposed over the metal layer such that a protruding segment of the metal layer acts as an interface between the conductive line and the metallization layer. The conductive line is copper (Cu) and the metal layer is ruthenium (Ru). The Ru metal layer includes an upper metal layer section and a lower metal layer section.

Dual-metal ultra thick metal (UTM) structure

A method of forming a mandrel for use in a pitch doubling process is provided in which a metal hard mask is inserted between a mandrel material layer and a soft mask. The insertion of the metal hard mask allows for easier pattern transfer into the mandrel material layer and avoids many issues encountered during multi-patterning steps. The insertion of the metal hard mask forms a square mandrel that has a flat top due to durability against etch and ability to wet strip the metal hard mask. The metal hard mask can be tuned before pattern transfer into the underlying mandrel material layer to provide a hard mask pattern that is smaller or larger than the pattern without performing such tuning. The method also can be used to protect the downstream non-mandrel processes where selectivity is crucial.

Metal hard mask for precise tuning of mandrels

A semiconductor device is provided. The semiconductor device includes a memory including a bottom electrode, a magnetic tunnel junction (MTJ) stack on the bottom electrode, and an upper electrode on the MTJ stack. The semiconductor device also includes at least one dielectric layer formed around the memory, wherein a top metal layer contact hole is formed in the at least one dielectric layer, a dielectric liner layer formed in the top metal contact hole, and a top metal layer contact in the top metal layer contact hole.

MRAM top electrode structure with liner layer

A novel bevel etch sequence for embedded metal contamination removal from BEOL wafers is provided. In one aspect, a method of processing a wafer includes: performing a bevel dry etch to break up layers of contaminants with embedded metals which, post back-end-of line metallization, are deposited on a bevel of the wafer, which forms a damaged layer on surfaces of the wafer, and then performing a sequence of wet etches, following the bevel dry etch, to render the bevel of the wafer substantially free of contaminants, wherein the sequence of wet etches includes etching the damaged layer to undercut and lift-off any remaining contaminants. A wafer, processed in this manner, having a bevel that is substantially free of contaminants is also provided.

Embedded metal contamination removal from BEOL wafers

Embodiments disclosed herein describe methods of forming semiconductor devices. The methods may include etching vias and trenches in a middle-of-line (MOL) layer that has a low-k dielectric layer, a sacrificial nitride layer, and a hard mask layer. The methods may also include depositing a thin nitride layer within the via trench, depositing a carbon layer on the thin nitride layer within the vias and trenches, etching back the thin nitride layer to expose a portion of the hard mask layer, removing the hard mask layer and the carbon layer, and removing the thin nitride layer and the sacrificial nitride layer.

Hard mask removal without damaging top epitaxial layer

Methods of patterning vias and trenches using a polymerization protective liner after forming a lower patterned mask layer used for etching trenches on a semiconductor substrate prior to forming an upper patterned mask layer used for etching vias are provided. Methods involve forming a polymerization protective liner either nonconformally or conformally using silicon tetrachloride and methane polymerization. Polymerization protective liners may be sacrificial.

Polymerization protective liner for reactive ion etch in patterning

A semiconductor device is provided. The semiconductor device includes a base layer, a first MRAM device formed on the base layer, and a second MRAM device formed on the base layer. The first MRAM device has a different performance characteristic than the second MRAM device.

Same level MRAM stacks having different configurations

Techniques for area scaling of contacts in VTFET devices are provided. In one aspect, a VTFET device includes: a fin(s); a bottom source/drain region at a base of the fin(s); a gate stack alongside the fin(s); a top source/drain region present at a top of the fin(s); a bottom source/drain contact to the bottom source/drain region; and a gate contact to the gate stack, wherein the bottom source drain and gate contacts each includes a top portion having a width W1over a bottom portion having a width W2, wherein W2<W1, and wherein a sidewall along the top portion is discontinuous with a sidewall along the bottom portion. The bottom portion having the width W2is present alongside the gate stack and the top source/drain region. A method of forming a VTFET device is also provided.

Area scaling for VTFET contacts

A method of semiconductor manufacture comprising forming a plurality of first mandrels as the top layer of the multi-layered hard mask and forming a first spacer around each of the plurality of first mandrels. Removing the plurality of first mandrels and cutting the first spacer to form a plurality of second mandrels. Forming a second spacer around each of the plurality of second mandrels and forming a first self-aligned pattern that includes a plurality of third mandrels. Removing the plurality of second mandrels and the second spacer and etching the multi-layered hard mask to transfer the first-self aligned pattern to a lower layer of the multi-layered hard mask. Forming a second self-aligned pattern, wherein the second self-aligned pattern is intermixed with the first self-aligned pattern and etching the first self-aligned pattern and the second self-aligned pattern into the conductive metal layer.

Structure and method to pattern pitch lines

A top cap layer covering a first metal line and a second metal line, horizontally between the first metal line and the second metal line is, in sequential order, a post cap liner, an air gap and the post cap liner. A first set of metal lines embedded in an upper surface of a dielectric, a second set of metal lines embedded below the dielectric and above the electronic components, a post cap liner covering the first set of metal lines, a cavity which dissects a first metal line of the first set of metal lines and extends to a second metal line of the second set of metal lines and dissects the second set of metal lines. Forming a cavity in a first metal line embedded in an upper surface of a dielectric, where the first metal line and the dielectric are covered by a top cap layer.

Subtractive metal etch with improved isolation for BEOL interconnect and cross point

A redistribution layer for an integrated circuit package is provided. The redistribution layer includes a first conductive layer and a second layer disposed directly on the first conductive layer. The first conductive layer has a resistivity of less than 3.6*10Ω·m and has a thickness of greater than or equal to 1 μm. The second layer includes tungsten. An integrated circuit package is also provided that includes the redistribution layer electrically connecting a first integrated circuit of the first integrated circuit package to a first input/output of a frame of the integrated circuit package. The frame is connected to the first integrated circuit. A method for manufacturing a redistribution layer is also provided.

X-ray shielding structure for a chip

A device includes: a first dielectric material; a first metal line in the first dielectric material; a second dielectric material disposed on the first dielectric material and the first metal line; a second metal line in the second dielectric material; and a plurality of metal vias disposed on a same level and connecting the first metal line and the second metal line, wherein the plurality of metal vias comprise a first top via and a bottom via having different sidewall profile angles.

Dual color via patterning

Embodiments of the present invention are directed to fabrication methods and resulting structures having a back-end-of-line (BEOL) single damascene (SD) top via spacer defined by pillar mandrels. In a non-limiting embodiment of the invention, a first conductive line is formed in a first dielectric layer. A mandrel is formed over the first conductive line and a spacer is formed on a sidewall of the mandrel. A portion of a second dielectric layer is recessed to expose a top surface of the spacer and a top surface of the mandrel and the mandrel is removed. The spacer prevents damage to the second dielectric layer while removing the mandrel. The mandrel is replaced with a conductive material. A first portion of the conductive material defines a via and a second portion of the conductive material defines a second conductive line. The via couples the first conductive line to the second conductive line.

Back-end-of-line single damascene top via spacer defined by pillar mandrels

A method of forming a multi color resist structure includes providing a substrate including an underlayer material; forming a first organic planarizing layer on the substrate; forming a first anti reflecting layer on the first organic planarizing layer, forming and developing a first patterned resist on the first anti reflecting layer; forming a second organic planarizing layer on the first anti reflecting layer and on the first patterned resist; forming a second anti reflecting layer on the second organic planarizing layer and forming and developing the second patterned resist, wherein the first patterned resist is a non-chemically amplified resist (n-CAR) or metal resist and the second patterned resist is CAR organic resist.

Litho-litho-etch (LLE) multi color resist

A semiconductor structure includes a plurality of conductive lines formed within a dielectric, wherein each of the plurality of conductive lines electrically communicates with a respective contact, a metal layer disposed over each of the plurality of conductive lines, a phase change memory (PCM) element disposed over the metal layer of each of the plurality of conductive lines, and a projection liner encapsulating the PCM element. Spacers directly contact sidewalls of the projection liner and the PCM element includes a GeSbTe (germanium-antimony-tellurium or GST) layer.

Wrap-around projection liner for AI device

Growing community of inventors

Slingerlands, NY, United States of America

Yann Mignot