Sigma Designs, Inc.

Yann Le Cornec

Julien Tan Nguyen

Mark Hsu

Alain Doreau

Bernard Georges Fraenkel

This invention provides a method of pixel data compression in which sets of adjacent pixels are compressed in a manner which is sometimes lossy but which reserves the greatest loss of accuracy for circumstances where loss is masked by high frequency components of the original pixel data.

Compression of pixel data

A method and system for synchronizing to an incoming Hsync signal, and for generating a phase locked clock signal in response thereto. The Hsync signal and an incoming clock are coupled to a sequence of modules. Each module includes a latch for sampling the incoming clock on a transition of the Hsync signal, whose output is combined (using an XOR gate) with the Hsync signal. Each module includes a time delay for generating a delayed clock signal, incrementally delayed from the previous module in the sequence, so that the clock signal for each module is phase-offset from all other modules. The latch outputs are summed using a resistor network, to produce a triangle-shaped waveform which is phase locked to the Hsync signal and which is frequency locked to the incoming clock. The triangle-shaped waveform is compared with a constant voltage to produce a square wave.

Synchronizing to an input signal

An improved digital signal processor, in which arithmetic multiply-add instructions are performed faster with substantial accuracy. The digital signal processor performs multiply-add instructions with look-ahead rounding, so that rounding after repeated arithmetic operations proceeds much more rapidly. The digital signal processor is also augmented with additional instruction formats which are particularly useful for digital signal processing. A first additional instruction format allows the digital signal processor to incorporate a small constant immediately into an instruction, such as to add a small constant value to a register value, or to multiply a register by a small constant value; this allows the digital signal processor to conduct the arithmetic operation with only one memory lookup instead of two. A second additional instruction format allows the digital signal processor to loop back to a location relatively addressed from the looping instructions; this allows the digital signal processor to conduct the loop operation with only one memory lookup instead of two.

Accurate high speed digital signal processor

An improved audio-output device coupleable to a computer system, in which a DSP operating under software control emulates a common command interface. The command interface has a set of registers that are made available to the CPU for reading and writing, even if there are no such physical registers available in the device. The DSP also performs tasks in addition to audio-output, even though the audio-output device is required to respond immediately to commands from the CPU. The audio-output device has a DSP for interpreting and executing commands received from the CPU, a local memory for storing data input to or output from the DSP, a bus-interface (BIF) element for coupling the DSP and memory to a system bus, and a direct memory access (DMA) element for transferring data between the local memory and the system bus. The local memory has an emulation region for emulating a set of named registers the CPU may read from and write into according to the command interface, and a communication region for transmitting messages between the CPU and the DSP. The emulation region is indicated by a base register and a set of offset values, and has a dynamically allocated set of registers for emulating the set of named registers the CPU may read from and write into.

Sound board emulation using digital signal processor

A method for decoding and displaying video signals using a memory buffer, in which a speed of a write operation for a memory buffer is adjusted to avoid overtaking a read operation for the same memory buffer. A display controller and a video MPEG engine contend for access to a DRAM memory buffer controller, and have their relative priorities set so that the video MPEG engine operates to write to the memory buffer at a relatively slow speed during a time period when the display controller is reading from that same memory buffer, and to write to the memory buffer at a relatively fast speed during a time period when the display controller is not reading from the memory buffer. The relatively slow speed is preferably much slower than the reading speed of the display controller, while the relatively fast speed is preferably much faster than the display controller. The DRAM memory buffer controller has a limited memory transfer bandwidth; the display controller and the video MPEG engine are operated at speeds which completely occupy that bandwidth, with the display controller given higher priority. Thus, while the display controller is reading from the memory buffer, the video MPEG engine is constrained to operate at a relatively slow speed, and is unable to overtake the display controller, but while the display controller is not reading from the memory buffer (e.g., during a vertical retrace interval), the video MPEG engine is able to operate at a relatively high speed, and is able to write an entire frame to the memory buffer in a relatively short time.

Growing community of inventors

Fremont, CA, United States of America

Yann Le Cornec