Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Commissariat a L'energie Atomique

Stmicroelectronics S.a.

Yann Lamy

Lamine Benaissa

Etienne Navarro

Bernard Viala

Sylvain Joblot

Laurent Dussopt

Luca Perniola

Guy-Michel Parat

Jean-Philippe Michel

Olivier Guiller

Ossama El Bouayadi

Assia Tria

Amazir Moknache

Alain Merle

Anne-Sophie Royet

A semiconductor on insulator type substrate, comprising at least: in which the trap rich layer comprises at least one first region and at least one second region adjacent to each other in the plane of the trap rich layer, the material of the at least one first region being in an at least partially recrystallized state and having an electrical resistivity less than that of the material in the at least one second region.

SOI substrate compatible with the RFSOI and FDSOI technologies

A method for producing a capacitor stack in one portion of a substrate, the method including: forming a cavity along a thickness of the portion of the substrate from an upper face of the substrate, depositing a plurality of layers contributing to the capacitor stack onto the wall of the cavity and onto the surface of the upper face, and removing matter from the layers until the surface of the upper face is reached. The forming of the cavity includes forming at least one trench and, associated with each trench, at least one box. The at least one trench includes a trench outlet that opens into the box. The box includes a box outlet that opens at the surface of the upper face, and the box outlet being shaped to be larger than the trench outlet.

Method for producing a capacitor

RF transmission device including at least:

Device for radiofrequency (RF) transmission with an integrated electromagnetic wave reflector

A TSV via structure comprising an upper part made on the side of the front face of a substrate in which electronic components are located and a lower part with height and cross-section smaller than the height and cross-section the upper part, the arrangement of the connection element in the substrate being such that it releases stresses generated by the different materials of said structure.

TSV via provided with a stress release structure and its fabrication method

An electronic chip including an integrated circuit arranged a face of a substrate, and a protection device arranged partially facing the integrated circuit is provided. The protection device includes a capacitor having a first electrode and a second electrode between which a layer of phase change material is disposed changing locally from a first resistive state to a second resistive state different from the first state by penetration of a beam. The first state is an amorphous state wherein the capacitor has a first capacitance and/or a first resistance and the second state is a crystalline state wherein the capacitor has a second capacitance and/or a second resistance different from the first capacitance and first resistance. The protection device is electrically connected to the integrated circuit by at least one of the first or second electrodes so that the integrated circuit measures the resistance and/or capacitance of the capacitor.

Chip comprising a phase change material based protecting device and a method of manufacturing the same

An electronic chip is provided, including an electronic circuit located at a front face of a substrate; a capacitive element placed at a back face of the substrate and facing the electronic circuit, and electrically connected to the electronic circuit by a first electrical connection and a second electrical connection, the first electrical connection including at least a first electrically conducting via passing through the substrate, the electronic circuit being configured to measure a value of electrical capacitance of the capacitive element between the first and the second electrical connections; and a plurality of second vias or trenches passing through the back face of the substrate and a part of the thickness of the substrate, and extending toward the electronic circuit such that bottom walls of the plurality of second vias or trenches are separated from the electronic circuit by at least one non-zero distance.

Electronic chip with means of protecting its back face

The integrated microelectronics component comprises an electric conductor forming a transmission line element for a radio frequency electromagnetic wave. This electric conductor is surrounded at least partially by a preferably closed magnetic circuit, formed at least by superposition of a layer of ferromagnetic material having a saturation magnetization value greater than or equal to 800 kA/m and of a layer of magnetic material. The layer of magnetic material then generates a uniaxial magnetic anisotropy in the adjacent ferromagnetic layer. A high magnetization can then be combined with a high anisotropy, thus enabling operation in high frequency ranges, for example about 5 to 20 GHz.

Growing community of inventors

Saint Etienne de Crossey, France

Yann Lamy