Commissariat a L'energie Atomique Et Aux Energies Alternatives

Commissariat À L'énergie Atomique Et Aux Énergies Alternatives

Yann Bogumilowicz

Jean-Marc Fedeli

Jean-Michel Hartmann

Charles Baudot

Fabrice Nemouchi

Philippe Rodriguez

Elodie Ghegin

Rami Khazaka

Thomas Magis

Pierre Brianceau

Herve Boutry

Alexis Abraham

Ségolène Olivier

Ségoléne Olivier

Thomas Jouanneau

A process for fabricating a heterostructure includes at least one elementary structure made of III-V material on the surface of a silicon-based substrate successively comprising: producing a first pattern having at least a first opening in a dielectric material on the surface of a first silicon-based substrate; a first operation for epitaxy of at least one III-V material so as to define at least one elementary base layer made of III-V material in the at least first opening; producing a second pattern in a dielectric material so as to define at least a second opening having an overlap with the elementary base layer; a second operation for epitaxy of at least one III-V material on the surface of at least the elementary base layer made of III-V material(s) so as to produce the at least elementary structure made of III-V material(s) having an outer face; an operation for transferring and assembling the at least photonic active elementary structure via its outer face, on an interface that may comprise passive elements and/or active elements, the interface being produced on the surface of a second silicon-based substrate; removing the first silicon-based substrate and the at least elementary base layer located on the elementary structure.

Method for fabricating a heterostructure comprising active or passive elementary structure made of III-V material on the surface of a silicon-based substrate

The present invention relates to a method for producing an element of a microelectronic device on a support comprising a base layer, an inserted layer and a covering layer. The method includes forming a confinement volume including an etching of the inserted layer selectively to the base layer and to the covering layer, and filling, by a filling material constituting the element, of at least one part of the confinement volume by an epitaxial growth of the material from the side wall. The formation of the confinement volume comprises a formation of a hole through the whole thickness of the covering layer, and the etching is an anisotropic etching done by applying an etching on the inserted layer through the hole.

Method of producing an element of a microelectronic device

First, second and third series of samples are successively made so as to determine the influence of the deposition parameters on the crystallographic quality of a layer of semiconductor material of III-V type. The parameters studied are successively the deposition pressure, the deposition temperature and the deposited thickness of a sub-layer of semiconductor material of III-V type so as to respectively determine a first deposition pressure, a first deposition temperature at the first deposition pressure, and a first deposited thickness at the first deposition temperature and at the first deposition pressure. The sub-layer of semiconductor material of III-V type is thickened by ways of a second layer of semiconductor material of III-V type deposited under different conditions.

Method for determining preferential deposition parameters for a thin layer of III-V material

A method of manufacturing an optical waveguide with a vertical slot including the steps of a) providing a substrate successively including an electric insulator layer and a crystalline semiconductor layer, b) forming a trench on the semiconductor layer to expose the electric insulator layer and defining first and second semiconductor areas on either side, step b) being executed so that the first semiconductor area has a lateral edge extending across the entire thickness of the semiconductor layer, c) forming the dielectric layer having the predetermined width across the entire thickness of the lateral edge, the method being remarkable in that the trench formed at step b) is configured so that the second semiconductor area forms a seed layer.

Optical waveguide manufacturing method

Fabrication of a photodetector is performed on a substrate comprising a first portion successively provided with a first semiconductor film, an electrically insulating layer, a second semiconductor film, and a protection layer. The substrate also comprises a second portion not comprising the second semiconductor film. It further comprises a third portion not comprising the second semiconductor film and the protection layer. The second semiconductor film is etched in the first portion to form a cavity. A PIN/NIP diode is formed in the third portion at least by means of deposition of a third semiconductor material which also comes and fills the cavity. A conversion layer is deposited to absorb a light signal originating from the second semiconductor film and to convert the light signal into an electric signal, the conversion layer electrically connecting the PIN/NIP diode.

Method for fabricating a photodetector

The process for smoothing a rough surface of a first substrate made of a semiconductor alloy based on at least two elements chosen from Ga, As, Al, In, P and N is implemented by placing a second substrate facing the first substrate so that the rough surface is placed facing a surface of the second substrate. The first and second substrates are separated by a distance d of at least 10 &#x3bc;m, the facing portions of the two substrates defining a confinement space. The first substrate is then heated so as to partially desorb one of the elements of said alloy and to reach the saturated vapor pressure of this element in the confinement space and to obtain a surface atom mobility that is sufficient to reduce the roughness of the rough surface.

Growing community of inventors

Grenoble, France

Yann Bogumilowicz