International Business Machines Corporation

Adeia Semiconductor Bonding Technologies Inc.

Adeia Semiconductor Solutions LLC

Yann A M Mignot

Sean David Burns

Lawrence Alfred Clevenger

Sivananda K Kanakasabapathy

Christopher J Penny

Chi-Chun Liu

Roger Allan Quon

Nicole A Saulnier

Nelson M Felix

Matthew Earl Colburn

Stuart A Sieg

Isabel C Estrada-Raygoza

Yongan Xu

Anuja E DeSilva

Chih-Chao Yang

Hemanth Jagannathan

Hao Tang

Kisup Chung

John Christopher Arnold

Theodorus E Standaert

Ekmini Anuja De Silva

Xuefeng Liu

Victor W C Chan

Indira P V Seshadri

Hsueh-Chung Chen

Sean D Burns

A method for forming fins includes forming a three-color hardmask fin pattern on a fin base layer. The three-color hardmask fin pattern includes hardmask fins of three mutually selectively etchable compositions. Some of the fins of the first color are etched away with a selective etch that does not remove fins of a second color or a third color and that leaves at least one fin of the first color behind. The fins of the second color are etched away. Fins are etched into the fin base layer by anisotropically etching around remaining fins of the first color and fins of the third color.

Alternating hardmasks for tight-pitch line formation

A semiconductor structure includes a multilayer structure having a first layer and a second layer disposed on the first layer. The semiconductor structure further includes at least a first via extending from a top of the second layer to a top of a first metal contact disposed in the first layer. A polymer film is disposed on at least a portion of sidewalls of the first via.

Via cleaning to reduce resistance

Methods of forming fins include masking a region on a three-color hardmask fin pattern, leaving a fin of a first color exposed. The exposed fin of the first color is etched away with a selective etch that does not remove fins of a second color or a third color. The mask and all fins of a second color are etched away. Fins are etched into a fin base layer using the fins of the first color and the fins of the third color.

A capacitor includes a stack. The stack has a first metallic layer formed over a substrate, an insulator formed over the first metallic layer, and a second metallic layer formed over the insulator. The first metallic layer has at least one high domain and at least one low domain, where a surface of the substrate in the at least one low domain has a height that is lower than a surface of the substrate in the at least one high domain.

Efficient metal-insulator-metal capacitor

An interconnect structure having a pitch of less than 40 nanometers and a self-aligned quadruple patterning process for forming the interconnect structure includes three types of lines: a &#x3b2; line defined by a patterned bottom mandrel formed in the self-aligned quadruple patterning process; a &#x3b3; line defined by location underneath a top mandrel formed in the self-aligned quadruple patterning process; and an &#x3b1; line defined by elimination located underneath neither the top mandrel or the bottom mandrel formed in the self-aligned quadruple patterning process. The interconnect structure further includes multi-track jogs selected from a group consisting of a &#x3b2;&#x3b3;&#x3b2; jog; a &#x3b2;&#x3b1;&#x3b2; jog; an &#x3b1;&#x3b2;&#x3b3; jog; a &#x3b3;&#x3b2;&#x3b1; jog, and combinations thereof. The first and third positions refer to the uncut line and the second position refers to the cut line in the self-aligned quadruple patterning process.

Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogs

Capacitors include a stack that has a first metallic layer formed over a substrate with at least one high domain and at least one low domain, an insulator formed over the first metallic layer, and a second metallic layer formed over the insulator. A bottom contact is formed in the substrate having a top surface that is even with a top surface of the substrate in the at least one high domain. A cap layer is formed directly on the substrate in the high domains, under the stack.

A method includes forming at least a first via in a multilayer structure comprising a first layer and a second layer formed over the first layer, the first via extending from a top of the second layer to a top of a first contact formed in the first layer and forming a polymer film on at least a portion of sidewalls of the first via by etching the top of the first contact using a cleaning process.

An interconnect structure having a pitch of less than 40 nanometers and a self-aligned quadruple patterning process for forming the interconnect structure includes three types of lines: a &#x3b2; line defined by a patterned bottom mandrel formed in the self-aligned quadruple patterning process; a &#x3b3; line defined by location underneath a top mandrel formed in the self-aligned quadruple patterning process; and an &#x3b1; line defined by elimination located underneath neither the top mandrel or the bottom mandrel formed in the self-aligned quadruple patterning process. The interconnect structure further includes multi-track jogs selected from a group consisting of a &#x3b2;&#x3b3;&#x3b2; jog; a &#x3b2;&#x3b1;&#x3b2; jog; and &#x3b1;&#x3b2;&#x3b3; jog; a &#x3b3;&#x3b2;&#x3b1; jog, and combinations thereof. The first and third positions refer to the uncut line and the second position refers to the cut line in the self-aligned quadruple patterning process.

A method for forming fins includes forming a three-color hardmask fin pattern on a fin base layer. The three-color hardmask fin pattern has hardmask fins of three mutually selectively etchable compositions. A region on the three-color hardmask fin pattern is masked, leaving one or more fins of a first color exposed. All exposed fins of the first color are etched away with a selective etch that does not remove fins of a second color or a third color. The mask and all fins of a second color are etched away. Fins are etched into the fin base layer by anisotropically etching around remaining fins of the first color and fins of the third color.

A method for forming conductive lines comprises forming a hardmask on an insulator layer, a planarizing layer on the hardmask, and a hardmask on the planarizing layer, removing exposed portions of a layer of sacrificial mandrel material to form first and second sacrificial mandrels on the hardmask, and depositing a layer of spacer material in the gap, and over exposed portions of the first and second sacrificial mandrels and the hardmask. Portions of the layer of spacer material are removed to expose the first and second sacrificial mandrels. A filler material is deposited between the first and second sacrificial mandrels. A portion of the filler material is removed to expose the first and second sacrificial mandrels. Portions of the layer of spacer material are removed to expose portions of the hardmask. A trench is formed in the insulator layer, and the trench is filled with a conductive material.

Self aligned conductive lines with relaxed overlay

Embodiments are directed to a method of forming a semiconductor device and resulting structures having a hard masks for sidewall image transfer (SIT) block patterning. The method includes forming a first hard mask on a substrate. Spacers are formed on the first hard mask, and a second hard mask is formed over the spacers. The second hard mask and a portion of the first hard mask are concurrently removed by the same hard mask removal process to expose a surface of the substrate. After concurrently removing the second hard mask and portions of the first hard mask, the heights of the spacers are substantially equal.

Growing community of inventors

Slingerlands, NY, United States of America

Yann A M Mignot