Sandisk Technologies Inc.

International Business Machines Corporation

Intel Corporation

Globalfoundries Inc.

Western Digital Technologies, Inc.

Yanli Zhang

Johann Alsmeier

Raghuveer S Makala

Senaka Kanakamedala

James K Kai

Rahul Sharangpani

Yao-Sheng Lee

Geng Wang

Chengwen Pei

Jin Liu

Fei Zhou

Peng Zhang

George Matamis

Yingda Dong

Paul Christian Parries

Zhixin Cui

Murshed Chowdhury

Masatoshi Nishikawa

Wei Zhao

Ashish Kumar Baraskar

Jixin Yu

Akihiro Takagi

Jeffrey Bowman Johnson

Ching-Huang Lu

Joseph Ervin

Satoshi Shimizu

Adarsh Rajashekhar

Xiying Costa

Masanori Tsutsumi

Shinsuke Yada

Sateesh Koka

Daxin Mao

Yan Li

Liang Pang

Maximino Vasquez

Zhenyu Lu

Kevin McStay

Masaaki Higashitani

Xiang Yang

Jayavel Pachamuthu

John Joseph Pekarik

Jiahui Yuan

Hiroyuki Kinoshita

Henry Chien

William F Clark, Jr

Yun Shi

Achintya K Bhowmik

Kangguo Cheng

Qizhi Liu

Jian Feng Chen

Hiroyuki Ogawa

Peter Rabkin

Liang Li

Huai-Yuan Tseng

George Samachisa

Tong Zhang

Seh Kwa

David Michael Fried

Gregory Gower Freeman

Michiaki Sano

Andrew C Lin

Seiji Shimabukuro

Kwang-Ho Kim

Ramy Nashed Bassely Said

Kam Leung Lee

Gan Wang

Brian W Messenger

Genta Mizuno

Deepanshu Dutta

Dana Lee

Ming Hsi Wang

Pranita Kulkarni

Steven Theodore Sprouse

Andrei Mihnea

Roger Allen Booth, Jr

Dengtao Zhao

Fumiaki Toyama

Takashi Whitney Orimoto

Ravi Mahendra Todi

Srikanth Kambhatla

Jun Shi

Zhiming Zhuang

Tatsuya Hinoue

Akio Nishida

Kiyohiko Sakakibara

Sarath Chandran Puthenthermadam

Yuki Mizutani

Zhongguang Xu

Jiacen Guo

Naoki Takeguchi

Koichi Matsuno

Kensuke Yamaguchi

Somesh Peri

Sunil K Jain

Naohiro Hosoda

Takaaki Iwai

Xuan Tian

Teruo Okina

John Lang

Anil Nanduri

The memory device includes a memory block with memory cells arranged in word lines that are divided into sub-blocks. Control circuitry is configured to program each of the word lines of a selected sub-blocks in a plurality of program loops. During at least one program loop, the control circuitry applies a programming pulse to a selected word line. The control circuitry is also configured to simultaneously apply a verify voltage to the selected word line and a pass voltage to unselected word lines. In a first phase of a multi-phase pre-charge process, the control circuitry reduces the voltages applied to the selected word line and at least one unprogrammed word line to a low voltage. In a second phase that follows the first phase, the control circuitry reduces the voltages applied to all word lines that remained at the pass voltage to the low voltage.

Channel pre-charge process in a memory device

A semiconductor structure includes a vertical stack of repetition units, where each instance of the repetition unit extends along a first horizontal direction and includes a first electrically conductive strip, a first memory film located over the first electrically conductive strip, discrete semiconductor channels that are laterally spaced apart from each other along the first horizontal direction and located above the first memory film, a second memory film located above the discrete semiconductor channels, a second electrically conductive strip located above the second memory film, and an insulating strip located above the first electrically conductive strip. Source/drain openings are arranged along the first horizontal direction, interlaced with the discrete semiconductor channels, and vertically extending through the vertical stack of repetition units, and source/drain pillar structures are located in respective source/drain openings, and vertically extending through the vertical stack of repetition units.

Three-dimensional nor array and method of making the same

A non-volatile memory device for performing compute in memory operations for a neural network uses a three dimensional NOR architecture in which vertical NOR strings are formed of multiple memory cells connected in parallel between a source line and a bit line. Weights of the neural network are encoded as threshold voltages of the memory cells and activations are encoded as word line voltages applied to the memory cells of the NOR strings. The memory cells are operated in the subthreshold region, where the word line voltages are below the threshold voltages. The NOR structure naturally sums the resultant subthreshold currents of the individual memory cells to generate the product of the activations and the weights of the neural network by concurrently applying input voltages to multiple memory cells of a NOR string.

Compute in memory three-dimensional non-volatile nor memory for neural networks

A stack of alternating layers of dielectric and conductive materials are formed on a substrate. A first portion of the stack of alternating layers forms a plurality of blocks of NAND memory. A second portion of the stack of alternating layers forms a configurable capacitor structure. The configurable capacitor structure is configurable to form one or more capacitors of configurable capacitance.

Configurable capacitors with 3D non-volatile array

A semiconductor structure includes a semiconductor substrate containing a shallow trench isolation structure that laterally surrounds a transistor active region, at least one line trench vertically extending into the semiconductor substrate, and a source region and a drain region located in the transistor active region. A contoured channel region continuously extends from the source region to the drain region underneath the at least one line trench. A gate dielectric contacts all surfaces of the at least one line trench and extends over an entirety of the contoured channel region. A gate electrode containing at least one fin portion overlies the gate dielectric.

Field effect transistors with gate fins and method of making the same

A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening fill structure including a vertical semiconductor channel and a memory film. The memory film includes a tunneling dielectric layer in contact with the vertical semiconductor channel, a first vertical stack of first dielectric oxide material portions located at levels of the insulating layers and including a dielectric oxide material of a first element, and a second vertical stack of second dielectric oxide material portions located at levels of the electrically conductive layers and including a mixed dielectric oxide material that is a dielectric oxide material of the first element and a second element.

Memory device including mixed oxide charge trapping materials and methods for forming the same

Technology is disclosed herein for preventing erase disturb in NAND. Erase voltages are applied to a source line and bit lines associated with selected memory cells, while applying an erase enable voltage to word lines connected to the selected cells. Preventing erase disturb may include raising the channel potential of unselected memory cells to a source line voltage that has a sufficiently low magnitude to not erase the unselected cells given a voltage on word lines connected to the unselected cells. The unselected cells share bit lines with the selected cells and may also share word lines. Preventing erase disturb may also include applying voltages to the select transistors that prevent the erase voltage from passing from the shared bit lines to the channels of the unselected cells. The voltages decrease from the bit lines to the unselected memory cells and may prevent GIDL generation. Current consumption is kept low.

Preventing erase disturb in NAND

A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a semiconductor material layer, an inter-tier dielectric layer, and a second alternating stack of second insulating layers and second electrically conductive layers located over the inter-tier dielectric layer. A memory opening vertically extends through the second alternating stack, the inter-tier dielectric layer, and the first alternating stack. A memory opening fill structure is located in the memory opening, and includes a first vertical semiconductor channel, a second vertical semiconductor channel, and an inter-tier doped region located between the first and the second semiconductor channel, and providing a first p-n junction with the first vertical semiconductor channel and providing a second p-n junction with the second vertical semiconductor channel.

Three dimensional memory device containing dummy word lines and p-n junction at joint region and method of making the same

To provide more test data during the manufacture of non-volatile memories and other integrated circuits, machine learning is used to generate virtual test values. Virtual test results are interpolated for one set of tests for devices on which the test is not performed based on correlations with other sets of tests. In one example, machine learning determines a correlation study between bad block values determined at die sort and photo-limited yield (PLY) values determined inline during processing. The correlation can be applied to interpolate virtual inline PLY data for all of the memory dies, allowing for more rapid feedback on the processing parameters for manufacturing the memory dies and making the manufacturing process more efficient and accurate. In another set of embodiments, the machine learning is used to extrapolate limited metrology (e.g., critical dimension) test data to all of the memory die through interpolated virtual metrology data values.

Virtual metrology for feature profile prediction in the production of memory devices

A memory device includes a semiconductor channel, a gate electrode, and a stack located between the semiconductor channel and the gate electrode. The stack includes, from one side to another, a first ferroelectric material portion, a second ferroelectric material portion, and a gate dielectric portion that contacts the semiconductor channel.

Memory device using a multilayer ferroelectric stack and method of forming the same

A three-dimensional memory device includes an alternating stack of insulating layers and word-line-level electrically conductive layers located over a substrate, and a vertical layer stack located over the alternating stack, the vertical layer stack including an insulating cap layer, drain select electrodes, and a drain-select-level insulating layer. The drain select electrodes are laterally spaced apart from each other by drain-select-level isolation structures. Memory stack structures including a respective vertical semiconductor channel and a respective memory film vertically extend through the alternating stack and the vertical layer stack. Each of the vertical semiconductor channels includes a word-line-level semiconductor channel portion extending through the alternating stack, a connection channel portion contacting a top end of the word-line-level semiconductor channel, and a drain-select-level semiconductor channel portion vertically extending through the vertical layer stack.

Three-dimensional memory device containing on-pitch drain select level structures and methods of making the same

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, an array of memory opening fill structures located within an array of memory openings vertically extending through the alternating stack, and a drain-select-level isolation structure vertically extending through drain-select-level electrically conductive layers between two rows of memory opening fill structures. The drain-select-level isolation structure may comprise a low-k dielectric material or an air gap.

Three-dimensional memory device including low-k drain-select-level isolation structures and methods of forming the same

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located within a respective one of the memory openings, and at least one drain-select-level isolation structure vertically extending through at least a topmost electrically conductive layer among the electrically conductive layers. The at least one drain-select-level isolation structure may include wiggles and cut through upper portions of at least some of the memory opening fill structures, or may include a vertically-extending dielectric material portion and laterally-protruding dielectric material portions adjoined to the vertically-extending dielectric material portion and laterally protruding into lateral recesses located adjacent to the at least the topmost electrically conductive layer.

Three-dimensional memory device with wiggled drain-select-level isolation structure and methods of manufacturing the same

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory opening fill structures extending through the alternating stack, where each of the memory opening fill structures includes a vertical semiconductor channel, a tunneling dielectric layer, and a vertical stack of memory elements located at levels of the electrically conductive layers between a respective vertically neighboring pair of the insulating layers. Each of the memory elements is located at a level of a respective one of the electrically conductive layers between the respective vertically neighboring pair of the insulating layers. Each of the memory elements includes a first memory material portion, and a second memory material portion that is vertically spaced from the first memory material portion. The second memory material portion has a different material composition from the first memory material portion.

Three-dimensional memory array including dual work function floating gates and method of making the same

A three-dimensional memory device includes a source contact layer overlying a substrate, an alternating stack of insulating layers and electrically conductive layers located overlying the source contact layer, and a memory opening fill structure located within a memory opening extending through the alternating stack and the source contact layer. The memory opening fill structure includes a composite semiconductor channel and a memory film laterally surrounding the composite semiconductor channel. The composite semiconductor channel includes a pedestal channel portion having controlled distribution of n-type dopants that diffuse from the source contact layer with a lower diffusion rate provided by carbon doping and smaller grain sizes, or has arsenic doping providing limited diffusion into the vertical semiconductor channel. The vertical semiconductor channel has large grain sizes to provide high charge carrier mobility, and is free of or includes only a low concentration of carbon atoms and n-type dopants therein.

Three-dimensional memory device including a composite semiconductor channel and a horizontal source contact layer and method of making the same

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San Jose, CA, United States of America

Yanli Zhang