Sharp Laboratories of America, Inc

Other

Yanjun Ma

Yoshi Ono

Sheng Teng Hsu

David R Evans

Douglas James Tweet

Tingkai Li

Bruce Dale Ulrich

Hong Ying

Tue H Nguyen

Jer-shen Maa

Fengyan Zhang

Wei-Wei Zhuang

Hongning Yang

An integrated circuit metal oxide semiconductor device comprises a gate region and a dielectric layer positioned therein, wherein the dielectric layer is substantially free of germanium diffused therein from a silicon germanium layer of the device. The method comprises depositing a dummy replacement gate, subjecting the device to high temperature processing, removing the dummy gate, and then depositing a dielectric material and a final gate material within the formed gate region. Because the dielectric material is deposited after high temperature processing of the device, there is negligible diffusion of germanium into the dielectric material.

Integrated circuit metal oxide semiconductor transistor

A MFMOS one transistor memory structure for ferroelectric non-volatile memory devices includes a high dielectric constant material such as ZrO , HfO , Y O , or La O , or the like, or mixtures thereof, to reduce the operation voltage and to increase the memory window and reliability of the device.

MFMOS capacitors with high dielectric constant materials

A method of fabricating a sub-micron MOS transistor includes preparing a substrate, including isolating an active region therein; depositing a gate oxide layer; depositing a first selective etchable layer over the gate oxide layer; depositing a second selective etchable layer over the first selective etchable layer; etching the structure to undercut the first selective etchable layer; implanting ions in the active region to form a source region and a drain region; depositing and planarizing the oxide; removing the remaining first selective etchable layer and the second selective etchable layer; depositing a gate electrode; and depositing oxide and metallizing the structure. A sub-micron MOS transistor includes a substrate; and an active region, including a gate region having a length of less than one micron; a source region including a LDD source region; and a drain region including a LDD drain region.

Structure and method of making a sub-micron MOS transistor

A multilayer dielectric stack is provided which has alternating layers of a high-k material and an interposing material. The presence of the interposing material and the thinness of the high-k material layers reduces or eliminate effects of crystallization within the high-k material, even at relatively high annealing temperatures. The high-k dielectric layers are a metal oxide of preferably zirconium or hafnium. The interposing layers are preferably amorphous aluminum oxide, aluminum nitride, or silicon nitride. Because the layers reduce the effects of crystalline structures within individual layers, the overall tunneling current is reduced. Also provided are atomic layer deposition, sputtering, and evaporation as methods of depositing desired materials for forming the above-mentioned multilayer dielectric stack.

Method of forming a multilayer dielectric stack

Silicon-germanium MOSFET with deposited gate dielectric and metal gate electrode and method for making the same

A method of fabricating a dual metal gate CMOS includes forming a gate oxide in a gate region and depositing a place-holder gate in each of a n-well and p-well; removing the place-holder gate and gate oxide; depositing a high-k dielectric in the gate region; depositing a first metal in the gate region of the p-well; depositing a second metal in the gate region of each of the n-well and p-well; and insulating and metallizing the structure. A dual metal gate CMOS of the invention includes PMOS transistor and a NMOS transistor. In the NMOS, a gate includes a high-k cup, a first metal cup formed in the high-k cup, and a second metal gate formed in the first metal cup. In the PMOS, a gate includes a high-k cup and a second metal gate formed in the high-k cup.

Dual metal gate CMOS devices and method for making the same

Method of making MFMOS capacitors with high dielectric constant materials

A thin film structure includes a substantially single-phase, c-axis PGO film on an insulator for use in metal ferroelectric insulator semiconductor single transistor non-volatile memory applications. The PGO on insulator structure can also be used in capacitors, pyroelectric infrared sensors, optical displays, optical switches, piezoelectric transducers, and surface acoustic wave devices. In a preferred embodiment, the PGO film is deposited on a Zirconium Oxide insulator layer.

Single c-axis PGO thin film on ZrO2 for non-volatile memory applications and methods of making the same

A method of forming conducting diffusion barriers by depositing an initial film and implanting ions to modify the film is provided. An initial film having good step coverage is deposited over a semiconductor substrate. The initial material need not have the desired properties for a conducting diffusion barrier, but preferably contains one or more elements to be used in forming a desired film with the appropriate properties. The initial material is deposited by CVD, PECVD or IMP deposition. Ions are preferably implanted using plasma immersion ion implantation (PIII), although other methods are also provided. The method of the present invention produces binary, ternary, quaternary and other more complex films, while providing adequate step coverage.

Method of forming conducting diffusion barriers

A method of fabricating a dynamic threshold voltage metal oxide semiconductor (DTMOS) for operation at threshold voltages less than 0.6 volts includes preparing a silicon substrate to form a trench in an active area; forming a silicon layer in the trench; doping the silicon layer in the trench to form a highly doped layer, having a doping ion concentration in a range of between about 5.0&middot;10 cm and 5.0&middot;10 cm ; depositing a silicon layer over the high doped silicon layer; and completing the structure to form a DTMOS transistor.

Method of making a low leakage dynamic threshold voltage MOS (DTMOS) transistor

Multilayer dielectric stack and method

A method of plasma doping substrates is provided. The substrate is covered with photoresist and placed within a plasma chamber. A doping gas is introduced into the chamber and ionized. A dilutant gas is also introduced to provide better control of the total amount of dosage associated with a given duration of exposure. The dilutant gas is preferably monatomic to reduce, or eliminate, affects associated with pressure variations within the chamber caused by dissociation of elements within the plasma chamber. The dilutant gas preferably contains lighter elements so as to reduce, or eliminate, damage to the photoresist caused by ion impacts. The dilutant gas is preferably neon or helium. The present method provides a means to better control the dosage and reduce photoresist damage and contamination.

Dose control technique for plasma doping in ultra-shallow junction formations

A method of improving the electrical properties of high dielectric constant films by depositing an initial film and implanting oxygen ions to modify the film by decreasing the oxygen deficiency of the film while reducing or eliminating formation of an interfacial silicon dioxide layer. An initial high dielectric constant material is deposited over a silicon substrate by means of CVD, reactive sputtering or evaporation. Oxygen ions are preferably implanted using plasma ion immersion (PIII), although other methods are also provided. Following implantation the substrate is annealed to condition the high dielectric constant film.

Method for improving electrical properties of high dielectric constant films

A high-k dielectric films is provided, which is doped with divalent or trivalent metals to vary the electron affinity, and consequently the electron and hole barrier height. The high-k dielectric film is a metal oxide of either zirconium (Zr) or hafnium (Hf), doped with a divalent metal, such as calcium (Ca) or strontium (Sr), or a trivalent metal, such as aluminum (Al), scandium (Sc), lanthanum (La), or yttrium (Y). By selecting either a divalent or trivalent doping metal, the electron affinity of the dielectric material can be controlled, while also providing a higher dielectric constant material then silicon dioxide. Preferably, the dielectric material will also be amorphous to reduce leakage caused by grain boundaries. Also provided are sputtering, CVD, Atomic Layer CVD, and evaporation deposition methods for the above-mentioned, doped high dielectric films.

Doped zirconia, or zirconia-like, dielectric film transistor structure and deposition method for same

A high-k dielectric film is provided which remains amorphous at relatively high annealing temperatures. The high-k dielectric film is a metal oxide of either Zr or Hf, doped with a trivalent metal, such as Al. Because the film resists the formation of a crystalline structure, interfaces to adjacent films have fewer irregularities. When used as a gate dielectric, the film can be made thin to support smaller transistor geometries, while the surface of the channel region can be made smooth to support high electron mobility. Also provided are CVD, sputtering, and evaporation deposition methods for the above-mentioned, trivalent metal doped high dielectric films.

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Vancouver, WA, United States of America

Yanjun Ma