Cadence Design Systems, Inc.

Yanjuan Zhan

Zhehong Qian

Ying Nan Li

Xiaofei Li

Buying Du

Guangxi Ying

Xiaobo Zhang

Yuan Yuan Li

Wei Yuan

Liang Huo

Embodiments of the invention provide a novel structure of a high-bandwidth-memory command queue of a memory controller with external per-bank refresh and DRAM burst reordering. Where the external per-bank refresh removes some of the unpredictable nature of PBR commands and DRAM burst reordering provides for efficient utilization of memory bandwidth.

Structure of a high-bandwidth-memory command queue of a memory controller with external per-bank refresh and burst reordering

Embodiments of the invention provide a command-oriented method to lower power consumption of PHY during idle time periods. The idle time periods occur because HBM Commands have certain timing windows where there is no data transmission on DFI data signals between the memory controller and the PHY data slice. These windows may be utilized to power down the PHY data slice data path through DFI signal handshaking. In contrast to the conventional low power mode, this method provides an advanced low power mode that can further reduce power consumption in different modes at each suitable idle time based on different command types.

Command-oriented low power control method of high-bandwidth-memory system

Various embodiments provide for determining a delay of a data signal with respect to a data strobe signal within a memory system comprising a memory controller and a memory module. In particular, some embodiments adjust a phase between a data signal and a data strobe signal such that a data eye of the data signal arrives at a receiver latch of a memory module can be centered on a transition of the data strobe signal. By centering the data eye of the data signal with the transition of the data strobe signal, various embodiments can ensure that the data strobe signal transition falls between the leading and trailing edges of the data eye, which in turn permits the memory module to obtain correct data from the memory controller during a write operation.

Systems and methods for memory protocol training

A method to initiate Command Address (CA) training on High Memory Bandwidth is provided to optimize CA bus setup and hold times relative to the memory clock. HBM protocol does not define any way to support CA training, but defines a very high working frequency. The high frequency makes it very difficult to ensure the timing on CA Bus-Row/Column command bus and CKE. As such, executing CA training before any normal operation is necessary to ensure the best setup/hold timings. The CA training takes advantage of protocol based instructions to initialize and implement CA training.

Methods and systems for implementing high bandwidth memory command address bus training

Embodiments of the invention provide an approach to implement a single architecture to support high bandwidth memory of pseudo channel mode or legacy channel mode by using a single command channel and single data channel. An address mapping method forces each port transaction to alternatively split to two pseudo channels. Compared to the conventional pseudo channel architecture, the single architecture and pseudo channel rotation eliminates the need for duplicated command traffic logic, and a time division command arbitrator, which greatly reduces both control logic and power consumption of the circuits. Furthermore, pseudo channel rotation improves the utilization of memory bandwidth because the address mapping improves synchronization of the two pseudo channel traffics.

Architecture of single channel memory controller to support high bandwidth memory of pseudo channel mode or legacy mode

According to certain general aspects, the present embodiments relate to methods and apparatuses for performing read and write data path training in HBMs. In accordance with some aspects, embodiments configure HBM mode registers for read and write data path training using an IEEE 1500 interface is simpler than the traditional scenario. In accordance with other aspects, the logic for performing read and write data path training is independent from normal memory access functionality in the host, capable of independently interacting with a PHY core for performing read and write data path training.

Method and apparatus for high bandwidth memory read and write data path training

A method for minimizing skew in a High Bandwidth Memory (HBM) device is provided. The method includes grouping a plurality of information bits of the HBM device into at least two groups of information bits, wherein the plurality of information bits includes a plurality of data bits and a plurality of control bits, and the plurality of information bits are grouped such that each group of the at least two groups includes at least one control bit and the at least two groups form a byte of data. The method further includes delaying the plurality of information bits of each group of the at least two groups during a data transfer operation to minimize the skew between the at least two groups of information bits.

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Beijing, China

Yanjuan Zhan