Chengdu Monolithic Power Systems Co., Ltd.

Monolithic Power Systems, Inc.

Yanjie Lian

Ji-Hyoung Yoo

Daping Fu

Lei Zhang

Jin Xing

An LDMOS having multiple field plates and manufacturing method. The LDMOS has a semiconductor substrate with an upper surface, an interlayer dielectric layer with an upper surface, a gate conducting layer, a field plate barrier layer, a first field plate and a second field plate. The gate conducting layer has a plate portion and a channel portion, the height of the plate portion to the upper surface of the semiconductor substrate is greater than the height of the channel portion to the upper surface of the semiconductor substrate. The field plate barrier layer disposes in the interlayer dielectric layer between the plate portion and the drain. The first field plate disposes in the interlayer dielectric layer and extends from the field plate barrier layer through the interlayer dielectric layer to the upper surface of the interlayer dielectric layer. The second field plate disposes in the interlayer dielectric layer and extends from the field plate barrier layer through the interlayer dielectric layer to the upper surface of the interlayer dielectric layer.

LDMOS having multiple field plates and associated manufacturing method

A lateral DMOS having a well region, a source region, a drain region, a first gate region and a second gate region. The first gate region may be positioned atop a portion of the well region near the source region side. The second gate region may be formed in a portion of the well region near the drain region side. The second gate region includes a shallow trench isolation structure formed in a shallow trench opened from a top surface of the well region and extended vertically into the well region, and having a first sidewall contacting with the drain region or abut the drain region, and further having a second sidewall opposite to the first sidewall and laterally extended below the first gate region.

Lateral DMOS having reduced lateral size

A lateral diode with high breakdown voltage capability and a method for forming the lateral diode. The lateral diode has an anode, a cathode, a substrate having a first conductivity type, an epitaxial layer having formed on the substrate, a current region formed in the epitaxial layer and on the substrate, a first well coupled to the anode, a second well coupled to the cathode, a third well with light doping concentration formed beside the first well, and a guard ring with heavy doping concentration formed in the first well and beside the third well, and between the third well and the second well is a drift region, a lateral breakdown occurs in the third well, the drift region and the second well when a reverse voltage added on the lateral diode is equal to or higher than a breakdown voltage.

Lateral schottky diode with high breakdown voltage capability

An LDMOS device with sinker link. The LDMOS device has a buried layer, a first well region and a sinker linking the buried layer and the first well region. The LDMOS device has a trench with its upper portion surrounded by the first well region and its lower portion surrounded by the sinker. The trench is formed so that the sinker can be formed by ion implantation through the trench. The trench is filled with non-conductive material.

LDMOS device with sinker link

A bipolar junction semiconductor device and associated method of manufacturing, the bipolar junction semiconductor device has a P type substrate, a N type buried layer formed in the substrate, a P&#x2212; type first epitaxial layer formed on the buried layer, a P&#x2212; type second epitaxial layer formed on the first epitaxial layer, a PNP BJT unit formed in the first and second epitaxial layers at a first active area, a NPN BJT unit formed in the first and second epitaxial layers at a second active area and a first isolation structure of N type formed in the first and second epitaxial layers at an isolation area. The isolation area is located between the first active area and the second active area, the first isolation structure connected with the buried layer forms an isolation barrier.

Bipolar junction semiconductor device and method for manufacturing thereof

A method for forming a steeped oxide on a substrate is described: successively forming a first pad oxide layer, a nitride layer, a second pad oxide layer and a poly layer on the substrate; etching the poly layer to have an opening for the stepped oxide region; isotropically etching the second pad oxide layer to the nitride layer through the opening to form a stepped trench; isotropically etching the nitride layer to the first pad oxide layer through the opening to expand the stepped trench; filling the stepped trench with dielectric material to form a dielectric layer; planarizing the dielectric layer; removing the poly layer; removing the second pad oxide layer; removing the nitride layer; removing the portion of the first pad oxide layer uncovered by the dielectric layer such that the remaining first pad oxide layer together the remaining dielectric layer forms the stepped oxide.

Method for forming stepped oxide on a substrate

A high voltage PMOS replacing the lightly doped region of the drain region with a low voltage P-well adopted in the low voltage devices, so as to save a mask. In order to achieve the high breakdown voltage and the low on resistance, a thick gate oxide applied in the DMOS is inserted. The N-type well region surrounding the source region may be replaced by a low voltage N-well adopted in the low voltage device to further save a mask.

High voltage PMOS and the method for forming thereof

A high side DMOS provides high breakdown voltage with small termination area. The high side DMOS has three parts which may comprise a stair-field plate in the termination part of the poly gate.

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Chengdu, China

Yanjie Lian