Micron Technology Incorporated

Yanhua Bi

Jonathan Scott Parry

Luca Porzio

Reshmi Basu

Zhou Zhou

Li Xin Zhao

Methods, systems, and devices for data defragmentation control are described. A memory system may include one or more regions of logical addresses and a plurality of memory cells arranged according to a plurality of physical addresses. In some instances, data may be stored to one or more discontinuous physical addresses and it may be desirable rearrange the data to be within continuous physical addresses (e.g., it may be desirable to defragment the data). Accordingly, the data stored to the one or more discontinuous physical addresses may be arranged (e.g., rearranged) to be within continuous physical addresses based at least in part on a value stored to one or more registers of the memory system.

Data defragmentation control

Methods, systems, and devices for dynamic low power mode are described. An apparatus may include a memory device and a controller. The controller may receive a command to transition from a first power state to a second power state, the first power state associated with executing received command and the second power state associated with deactivating one or more components of the memory device. The controller may execute, while in the first power state, a set of operations associated with the transition from the first power state to second power state. The controller may determine whether a duration to execute the set of operations satisfies a delay duration between receiving the command and transitioning to the second power state from the first power state. The controller may transition from the first power state to the second power state based on determining whether the duration satisfies the delay duration.

Dynamic low power mode

Methods, systems, and devices for write booster pinning are described. In some examples, a memory device may receive one or more commands (e.g., write commands) while operating in a first mode (e.g., a write booster mode). Some write commands may include an indication to pin the data to one or more SLCs. For example, a first write command may be associated with first data and a first indicator and a second write command may be associated with second data. Both the first data and the second data may be written to one or more SLCs. When maintenance operations are performed on the SLCs, the second data may be moved (e.g., written) to one or more MLCs. Additionally or alternatively, the memory system may receive one or more commands to unpin data (e.g., the first data) such that it may be moved to one or more MLCs during subsequent maintenance operations.

Write booster pinning

Methods, systems, and devices for a memory system host data reset function are described. A reset operation may be performed to reset data in a memory system without erasing host data from the memory system. The memory system and a host system may perform the reset operation to sequentially reorder the data across pages and blocks of the memory system, mitigating holes in the data. The reset operation may enable sequentially reordering the data by performing refresh operations on the blocks and performing a subsequent garbage collection operation to consolidate the data within the pages of the refreshed blocks. The host system may reorganize the logical block addresses associated with the blocks and the memory system may perform the refresh operations and the garbage collection operations. The blocks may be refreshed according to an order of access frequency and according to a measure of performance impact on the memory system.

Memory system host data reset function

Methods, systems, and devices for memory system logical unit number (LUN) procedures are described. A memory system may receive an indication to convert a LUN for storing LBAs associated with an application from a first type to a second type, where the second type is associated with a higher performance defragmentation process than the first type. The memory system may perform defragmentation on data associated with the LUN based on converting the LUN to the second type. The memory system may determine whether the LBAs stored in the LUN are ordered based on the defragmentation, and the memory system may operate (e.g., execute) the application based on the LBAs being ordered.

Memory system logical unit number procedures

Methods, systems, and devices for host initiated garbage collection are described. In some examples, a user accessible application or public interface of a host system may initiate a garbage collection procedure for a memory system using one or more vendor commands. For example, the host system and the memory system may support a first vendor command to check a fragmentation status or fragmentation parameter of the of the memory system. Additionally, the host system and the memory system may support a second vendor command to initiate a garbage collection procedure at the memory system, or to interrupt an ongoing garbage collection procedure. The host system and the memory system may also support a third vendor command to check the status of an initiated garbage collection procedure.

Host initiated garbage collection

Methods, systems, and devices for techniques for memory zone size adjustment are described. A memory system may dynamically update the size of a stale zone configured to store data written during a write burst or write booster mode. The stale zone may be part of a first block of memory cells, and may retain data during a transfer operation, such as flush operation. The size of the stale zone may be updated in response to the memory system receiving a command, such as an unmap command. The size of the stale zone may be determined based on an available zone size, an amount of data indicated in the command, an amount of data indicated in the command that has been transferred to a second block of memory cells, or a combination thereof.

Techniques for memory zone size adjustment

Methods, systems, and devices for data organization for logical to physical table compression are described. The memory system may identify a region that includes one or more logical addresses associated with discontinuous corresponding physical addresses. The memory system may include a plurality of regions of logical addresses and a plurality of memory cells arranged according to a plurality of physical addresses. The memory system may determine a period of inactivity of access operations on the plurality of memory cells and rearrange, during the period of inactivity, information stored within the discontinuous corresponding physical addresses to be within continuous physical addresses of the plurality of physical addresses.

Data organization for logical to physical table compression

Methods, systems, and devices for techniques to reduce write amplification are described. A memory device may receive a write command from a host device and may determine that a quantity of commands stored in a buffer for execution by a memory array satisfies a first threshold. In some examples, the memory device may identify whether a write amplification parameter associated with the memory array satisfies a second threshold. The memory device may write data associated with the write command to the memory array using a first mode to write the data or a second mode to write the data based on determining that the quantity of commands satisfies the first threshold and/or identifying whether the write amplification parameter satisfies the second threshold. In some examples, the memory device may adjust a value of the first threshold or the second threshold or both based on the write amplification parameter.

Techniques to reduce write amplification

Methods, systems, and devices for data movement based on address table activity are described. A memory system may support a first type of data movement operation and a second type of data movement operation. The memory system may select between the first type of data movement operation and the second type of data movement operation for a region based on address table activity for the region.

Data movement based on address table activity

Methods, systems, and devices for dynamically tuning host performance booster thresholds are described. A memory system may include a set of memory devices and an interface configured to communicate commands with a host system coupled with the memory system. The interface may communicate commands to the memory system according to a first command mode associated with a logical address space including a plurality of regions and communicate commands according to a second command mode associated with physical memory address. The memory system may further include a controller that may determine a region activated for the second command mode, receive a first plurality of commands, determine, upon deactivating the region, a first threshold based on a first quantity of read commands serviced according to the second command mode. The controller may activate the region for the second command based on a second quantity of read commands received exceeding the first threshold.

Dynamically tuning host performance booster thresholds

Methods, systems, and devices for techniques for command sequence adjustment are described. A memory system or a host system may adjust an order of a set commands in a queue if the memory system or host system determines that a subset of the commands in the queue are part of a test mode, for example by determining whether each command of the subset corresponds to a same size of data. The set of commands may be reordered such that the subset of commands associated with the test mode are continuous or back-to-back. In some cases, the subset of commands associated with test mode may be reordered such that logical addresses (e.g., logical block addresses) of the subset of commands are continuous.

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Shanghai, China

Yanhua Bi