Yangtze Memory Technologies Co., Ltd.

Yanhong Wang

Wei Liu

Liang Chen

Zhiliang Xia

Wenxi Zhou

Kun Zhang

Yuancheng Yang

Hongbin Zhu

Cheng Gan

Yanwei Shi

Shiqi Huang

Ning Jiang

Three-dimensional (3D) memory devices and methods for forming the same are disclosed. In certain aspects, a 3D memory device includes a first semiconductor assembly, a second semiconductor assembly, and an inter-assembly bonding layer between the first semiconductor assembly and the second semiconductor assembly. The first semiconductor assembly includes a first array structure and a first periphery structure. The first array structure includes a first memory stack having a plurality of interleaved stack conductive layers and stack dielectric layers. The first periphery structure includes a plurality of first peripheral circuits electrically connected to the first memory stack. The second semiconductor assembly includes a second array structure and a second periphery structure. The second array structure includes a second memory stack having a plurality of interleaved stack conductive layers and stack dielectric layers. The second periphery structure includes a plurality of second peripheral circuits electrically connected to the second memory stack.

Three-dimensional memory devices having semiconductor assemblies bonded by bonding layer and methods for forming the same

In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a peripheral circuit. The second semiconductor structure includes an array of memory cells, and a plurality of bit lines coupled to the memory cells and each extending in a second direction perpendicular to the first direction. Each of the memory cells includes a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor. The vertical transistor includes a semiconductor body extending in the first direction, and a gate structure in contact with a plurality of sides of the semiconductor body. One end of the semiconductor body coupled to the storage unit is flush with the gate structure. A respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction. The array of memory cells is coupled to the peripheral circuit across the bonding interface.

Memory devices having vertical transistors and methods for forming the same

In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, a first bonding interface between the first semiconductor structure and the second semiconductor structure, and a second bonding interface between the second semiconductor structure and the third semiconductor structure. The first semiconductor structure includes a peripheral circuit. The second semiconductor structure includes a first array of memory cells. The third semiconductor structure includes a second array of memory cells. Each of the memory cells of the first and second arrays includes a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor. The first array of memory cells is coupled to the peripheral circuit across the first bonding interface. The second array of memory cells is coupled to the peripheral circuit across the first bonding interface and the second bonding interfaces.

In certain aspects, a memory device includes a memory cell including a vertical transistor, and a storage unit having a first end coupled to a first terminal of the vertical transistor. The vertical transistor includes a semiconductor body extending in a first direction, and a gate structure coupled to at least one side of the semiconductor body. The memory device also includes a metal bit line coupled to a second terminal of the vertical transistor via an ohmic contact and extending in a second direction perpendicular to the first direction. The memory device further includes a dielectric layer opposing the memory cell with the metal bit line positioned between the dielectric layer and the memory cell. The memory device further includes a conductor extending from the dielectric layer to couple to a second end of the storage unit.

A three-dimensional (3D) memory device includes a plurality of memory stacks arranged along a first direction, and a dummy block structure disposed between two adjacent memory stacks. Each memory stack includes a plurality of first conductive layers and a plurality of first dielectric layers alternately stacked along a second direction perpendicular to the first direction. A channel structure extends through the plurality of first conductive layers and the plurality of first dielectric layers along the second direction. A first isolation structure is disposed between the dummy block structure and one of the plurality of memory stacks. A substrate is disposed under the plurality of memory stacks, the dummy block structure, and the first isolation structure. A second isolation structure is disposed in the substrate extending along the second direction.

Three-dimensional memory device and method for forming the same

In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells. The second semiconductor structure includes a first peripheral circuit of the array of memory cells. The first peripheral circuit includes a first transistor. The first semiconductor structure or the second semiconductor structure further includes a second peripheral circuit of the array of memory cells. The second peripheral circuit includes a second transistor. The first peripheral circuit and the second peripheral circuit are stacked over one another.

Three-dimensional memory devices and methods for forming the same

In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and second semiconductor structures. The first semiconductor structure includes an array of NAND memory strings, a first peripheral circuit of the array of NAND memory strings including a first transistor, a polysilicon layer between the array of NAND memory strings and the first peripheral circuit, and a first semiconductor layer in contact with the first transistor. The polysilicon layer is in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a second semiconductor layer in contact with the second transistor. The second semiconductor layer is between the bonding interface and the second peripheral circuit. The polysilicon layer is between the first semiconductor layer and the second semiconductor layer.

In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and the second semiconductor structures. The first semiconductor structure includes an array of NAND memory strings, a first peripheral circuit of the array of NAND memory strings including a first transistor, a polysilicon layer between the array of NAND memory strings and the first peripheral circuit, and a first semiconductor layer in contact with the first transistor. The polysilicon layer is in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a second semiconductor layer in contact with the second transistor. The second semiconductor layer is between the bonding interface and the second peripheral circuit. The first semiconductor layer is between the polysilicon layer and the second semiconductor layer.

In certain aspects, a method for forming a three-dimensional (3D) memory device is disclosed. A first semiconductor structure including an array of NAND memory strings is formed on a first substrate. A second semiconductor structure including a recess gate transistor is formed on a second substrate. The recess gate transistor includes a recess gate structure protruding into the second substrate. The first semiconductor structure and the second semiconductor structure are bonded in a face-to-face manner, such that the array of NAND memory strings is coupled to the recess gate transistor across a bonding interface.

Peripheral circuit having recess gate transistors and method for forming the same

In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and the second semiconductor structures. The first semiconductor structure includes an array of NAND memory strings, a first peripheral circuit of the array of NAND memory strings including a first transistor, a polysilicon layer between the array of NAND memory strings and the first peripheral circuit, and a first semiconductor layer in contact with the first transistor. The polysilicon layer is in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a second semiconductor layer in contact with the second transistor. The second semiconductor layer is between the bonding interface and the second semiconductor layer. The polysilicon layer is between the first semiconductor layer and the second semiconductor layer.

In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells and a first semiconductor layer in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a second semiconductor layer, a first peripheral circuit of the array of memory cells including a first transistor in contact with a first side of the second semiconductor layer, and a second peripheral circuit of the array of NAND memory strings including a second transistor in contact with a second side of the second semiconductor layer opposite to the first side.

In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, a first bonding interface between the first semiconductor structure and the second semiconductor structure, and a second bonding interface between the second semiconductor structure and the third semiconductor structure. The first semiconductor structure includes an array of NAND memory strings and a first semiconductor layer in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a first peripheral circuit of the array of NAND memory strings including a first transistor, and a second semiconductor layer in contact with the first transistor. A third semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a third semiconductor layer in contact with the second transistor. The second semiconductor layer is between the first bonding interface and the first peripheral circuit. The second peripheral circuit is between the second bonding interface and the third semiconductor layer.

In certain aspects, a memory device includes an array of memory cells and a plurality of peripheral circuits coupled to the array of memory cells. The peripheral circuits include a first peripheral circuit including a recess gate transistor. The peripheral circuits also include a second peripheral circuit including a flat gate transistor.

In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a peripheral circuit. The second semiconductor structure includes an array of memory cells and a plurality of bit lines coupled to the memory cells and each extending in a second direction perpendicular to the first direction. Each of the memory cells includes a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor. The vertical transistor includes a semiconductor body extending in the first direction, and a gate structure in contact with two opposite sides of the semiconductor body in the second direction. A respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction. The array of memory cells is coupled to the peripheral circuit across the bonding interface.

In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a first semiconductor layer, an array of NAND memory strings, and a first peripheral circuit of the array of NAND memory strings. Sources of the array of NAND memory strings are in contact with a first side of the first semiconductor layer. The first peripheral circuit includes a first transistor in contact with a second side of the first semiconductor layer opposite to the first side. The second semiconductor structure includes a second semiconductor layer and a second peripheral circuit of the array of NAND memory strings. The second peripheral circuit includes a second transistor in contact with the second semiconductor layer.

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Wuhan, China

Yanhong Wang