Cypress Semiconductor Corporation

Yangzhong Xu

Helmut Puchner

Oliver Pohland

Jeong-Yeop Nahm

Methods for fabricating diffusion regions having steep concentration profiles within MOS devices while minimizing junction capacitance degradation are provided. In particular, methods are provided which include patterning a gate structure upon a semiconductor substrate and subsequently etching a recess in exposed portions of the substrate. In some cases, the method includes forming a first dopant region within the exposed portions prior to etching the recess. The method may additionally or alternatively include implanting a second set of dopants into portions of the semiconductor substrate bordering the recess. In either case, the method includes growing an epitaxial layer within the recess and implanting a third set of dopants into the semiconductor topography to form a second dopant region extending to a depth at least within the epitaxial layer. A resulting semiconductor topography includes a source/drain region comprising an upper portion consisting essentially of first dopants of a first conductivity type.

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Santa Clara, CA, United States of America

Yangzhong Xu