Micron Technology Incorporated

Yangsung Joo

Sugato Mukherjee

Greg A Blodgett

Hidekazu Noguchi

Jason M Brown

David L Pinney

Apparatuses and methods for a temperature dependent delay between a wordline off signal and deactivating the wordline are disclosed. Memory devices may have reduced reliability when operating at relatively cold temperatures, which may be due in part to an increase in the write recovery time while the inning for a wordline to deactivate remains relatively unaffected. In some embodiments of the present disclosure, a delay circuit is used to insert a temperature dependent delay between a wordline off command being issued and the wordline being deactivated. The delay circuit may increase the length of temperature dependent delay at relatively cold temperatures, and decrease the length of the delay at relatively warm temperatures.

Apparatuses and methods for DRAM wordline control with reverse temperature coefficient delay

Apparatuses and methods for a temperature dependent delay between a wordline off signal and deactivating the wordline are disclosed. Memory devices may have reduced reliability when operating at relatively cold temperatures, which may be due in part to an increase in the write recovery time while the timing for a wordline to deactivate remains relatively unaffected. In some embodiments of the present disclosure, a delay circuit is used to insert a temperature dependent delay between a wordline off command being issued and the wordline being deactivated. The delay circuit may increase the length of temperature dependent delay at relatively cold temperatures, and decrease the length of the delay at relatively warm temperatures.

There is provided a device including a PMOS differential amplifier and an NMOS differential amplifier. The NMOS differential amplifier is coupled to the PMOS differential amplifier. The device is configured to operate as an inverter when a supply voltage is below a predetermined threshold.

Low voltage CMOS differential amplifier

A low voltage CMOS differential amplifier is provided. More specifically, in one embodiment, a device comprising a differential pair is provided. A self-biased transistor and a component are coupled to the differential pair. At least one of the self-biased transistor and the component supply a current to the differential pair, wherein the component supplies substantially all of the current when the self-biased transistor is operating in a triode state.

In a dynamic random access memory device, an auto-refresh method comprises receiving a command for the memory device to operate in a half-density mode. This causes a remapping circuit to remap a first memory address bit to an unused memory address location. Using the new addressing scheme, an auto-refresh operation is performed on the memory array operating in the half-density mode without skipping refresh commands.

Non-skipping auto-refresh in a DRAM

A reference voltage generator uses a conventional forward junction voltage generating device and a conventional thermal generator to generate a thermal voltage. The forward junction voltage and the thermal voltages have respective thermal sensitivities that act oppositely to each other so that, when the forward junction voltage is combined with the thermal voltage to produce a reference voltage, the reference voltage is substantially insensitive to temperature. The forward junction voltage and the thermal voltage are combined to produce the reference voltage in a manner that avoids generating any voltage having a magnitude that is greater than the magnitude of the sum of the forward voltage and the thermal voltage.

Low supply voltage temperature compensated reference voltage generator and method

A low voltage CMOS differential amplifier is provided. More specifically, in one embodiment, there is provided a method of manufacturing a device comprising coupling a fixed biased transistor in parallel to a self-biased transistor and configuring the fixed biased transistor and the self-biased transistor to provide a current to a differential amplifier, wherein the fixed biased transistor is configured to provide current to the differential amplifier when the self-biased transistor is operating in a triode or cut-off region.

A low voltage CMOS differential amplifier is provided. More specifically, there is provided a device comprising a differential pair coupled to a first tail current transistor and to a component wherein the first tail current transistor is configured to provide a tail current to the differential pair and the component is configured to provide a tail current to the differential pair when the first tail current transistor is operating in a triode region or in a cut-off region.

A clock synchronization circuit receives an input clock signal along with current and future data signals. The clock synchronization circuit generates a phase shifted clock signal in response to the input clock signal, with the phase shifted clock signal having a phase shift relative to the input clock signal that is a function of the current and future data signals. The clock synchronization circuit may also generate a plurality of phase shifted clock signals, with each phase shifted clock signal having a respective phase shift that is a function of the current and future logic states of groups of the other data signals.

Method and circuit for adjusting the timing of output data based on the current and future states of the output data

A memory device equilibrates voltages in a bit line pair to a reduced voltage level. The reduced equilibrate voltage level can be achieved by separating the conventional equilibrate process so that the positive portion and the negative portion of the sense amplifier are equilibrated at different times. Bit line equilibration can be associated with either the equilibrate step associated with the positive portion of the sense amplifier or the equilibrate step associated with the negative portion of the sense amplifier.

Dual stage DRAM memory equalization

Circuits and methods for driving a DRAM sense amplifier having low threshold voltage PMOS transistors are described. The source terminal of a low VPMOS transistor is maintained at ground potential during DRAM standby mode. The source terminal of the low VPMOS transistor is raised to an intermediate supply voltage responsive to a transition from DRAM standby mode to either DRAM read mode, write mode, or refresh mode and prior to development of a differential voltage between the gate and drain terminals of the low VPMOS transistor. These circuits and methods advantageously limit current loss through the low VPMOS transistor when the differential voltage develops between the gate and drain terminals of that low VPMOS transistor and in the event of a word line and digital line short-circuit.

Driving a DRAM sense amplifier having low threshold voltage PMOS transistors

An isolation signal line in a memory device having a standby power mode is configured to be exclusively held as either a logic high or logic low during some portion of the standby power mode and as the other of the logic high and logic low during another portion of the standby power mode to prevent unnecessary switching every time the memory device operates in standby power mode. As a result, memory devices having an upper and lower array achieve true electrical isolation during standby power modes and, if a row-to-column short exists, standby power mode current leakage is cut in half as compared to non-isolated arrays. The switching current necessary to drive the isolation signal line to a bootstrapped logic high during such standby power mode times is likewise prevented. In other embodiments, methods, electronic systems, wafers and DRAM are taught.

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Boise, ID, United States of America

Yangsung Joo