Qualcomm Incorporated

Applied Materials, Inc.

Apple Inc.

Wells Fargo Bank, N.a.

Intel Corporation

Canon Kabushiki Kaisha

Canon U.s.a., Inc.

Yahoo! Inc.

Nanyang Technological University

Rubrik, Inc.

Beijing Voyager Technology Co., Ltd.

Wd Media, LLC

Irm LLC

Canon Virginia, Inc.

Canon Information and Imaging Solutions, Inc.

Yang Yang

Kartik Ramaswamy

Jing Jiang

Tao Luo

Joseph Binamira Soriaga

Gabi Sarkis

Heechoon Lee

Jamie Menjay Lin

Wanshi Chen

Peter S Gaal

Jing X Sun

Tingfang Ji

Peter Pui Lok Ang

Alexandros Manolakos

Kenneth S Collins

June Namgoong

Hung Dinh Ly

Changlong Xu

Hari Sankar

Chao Wei

Ying Wang

Bilal Sadiq

Andrew Nguyen

Shahid Rauf

Amir Said

Makesh Pravin John Wilson

Abhijit Basu Mallick

Pramit Manna

Wooseok Nam

Wei Jennifer Yang

Jing Zhu

James D Carducci

Yi Huang

Krishna Kiran Mukkavilli

Alexei Yurievitch Gorokhov

John Edward Smee

Ludovic Godet

Srinivas D Nemani

Jian Li

Jilei Hou

Rameshchandra Bhaskar Ketharaju

Rutger Meyer Timmerman Thijssen

Christopher G Lott

Tza-Jing Gung

Sony Akkarakaran

Hao Xu

Muhammad Nazmul Islam

Renqiu Wang

Sumeeth Nagaraja

Chong Li

Chih-Ping Li

Yingyong Qi

Leonid Dorf

Michael D Willwerth

Richard Charles Fovell

Junyi Li

Juan Montojo

Yan Zhou

Wei Zeng

Haitong Sun

George Cherian

Huilin Xu

Xiao Feng Wang

Taesang Yoo

Simone Merlin

Sundar Subramanian

Jing Lei

Youn Hyoung Heo

Raghu Narayan Challa

Michael Robert Rice

Yujian Zhang

Markus Dominik Mueck

Richard Charles Burbidge

Gwendolyn Denise Barriac

Srinivas Gandikota

Yi Liu

Sudeep K Palat

Farhad Meshkati

Youmin Wang

Mark Joseph Saly

Ning Bi

Edward Harrison Teague

Wei Yang

Saurabha Rangrao Tavildar

Honglei Miao

Douglas A Buchberger, Jr

Manu Gulati

Otman Adam Basir

Valentin Alexandru Gheorghiu

Praburam Gopalraja

Jeffrey W Anthis

Yue Lu

Rahul Malik

Michael Faerber

Donald Karanewsky

Qian Fu

Farhad K Moghadam

Lingkai Kong

Rudolph Van Der Merwe

Jie Yu

A method for optimizing the compilation of a machine learning model to be executed on target edge devices is provided. Compute nodes of a plurality of compute nodes are allocated to a compiler optimization process for a compiler of said machine learning model. The machine learning model has a compute graph representation having nodes that are kernel operators necessary to execute the machine learning model and edges that connect said kernel operators to define precedence constraints. A round of optimization is scheduled for the process amongst the allocated compute nodes. At each allocated compute node a sequencing and scheduling solution is applied per round to obtain a performance metric for the machine learning model. From each compute node the performance metric is received and a solution that has the best performance metric is identified and implemented for execution of the machine learning model on the target edge devices.

Distributed machine learning compiler optimization

Embodiments of the present disclosure relate to methods for depositing an amorphous carbon layer onto a substrate, including over previously formed layers on the substrate, using a plasma-enhanced chemical vapor deposition (PECVD) process. In particular, the methods described herein utilize a combination of RF AC power and pulsed DC power to create a plasma which deposits an amorphous carbon layer with a high ratio of sp3 (diamond-like) carbon to sp2 (graphite-like) carbon. The methods also provide for lower processing pressures, lower processing temperatures, and higher processing powers, each of which, alone or in combination, may further increase the relative fraction of sp3 carbon in the deposited amorphous carbon layer. As a result of the higher sp3 carbon fraction, the methods described herein provide amorphous carbon layers having improved density, rigidity, etch selectivity, and film stress as compared to amorphous carbon layers deposited by conventional methods.

Pulsed plasma (DC/RF) deposition of high quality C films for patterning

Methods and apparatus for forming an integrated circuit structure, comprising: delivering a process gas to a process volume of a process chamber; applying low frequency RF power to an electrode formed from a high secondary electron emission coefficient material disposed in the process volume; generating a plasma comprising ions in the process volume; bombarding the electrode with the ions to cause the electrode to emit electrons and form an electron beam; and contacting a dielectric material with the electron beam to cure the dielectric material, wherein the dielectric material is a flowable chemical vapor deposition product. In embodiments, the curing stabilizes the dielectric material by reducing the oxygen content and increasing the nitrogen content of the dielectric material.

Method for forming integrated circuit structures

A method includes providing, within an etch chamber, a base structure including a target layer disposed on a substrate, and an etch mask disposed on the target layer, dry etching, within the etch chamber, the target layer using thionyl chloride to obtain a processed base structure, and after forming the plurality of features. The processed base structure includes a plurality of features and a plurality of openings defined by the etch mask. The method further includes removing the processed base structure from the etch chamber. In some embodiments, the target layer includes carbon. In some embodiments, the dry etching is performed at a sub-zero degree temperature.

Dry etching with etch byproduct self-cleaning

Some embodiments are directed to a tuning circuit. The tuning circuit generally includes: a first impedance coupled between a first terminal and a second terminal of the tuning circuit, wherein the first terminal is coupled to a generator and the second terminal is coupled to a load; a second impedance coupled between the first impedance of the tuning circuit and a reference potential node; and a signal path coupled to the first impedance or the second impedance, the signal path comprising an inductive element and a first switch coupled to the inductive element, wherein a control input of the first switch is coupled to a control input of the tuning circuit configured to receive a control signal associated with a pulsed voltage (PV) waveform.

Radio-frequency (RF) matching network for fast impedance tuning

An apparatus for generating plasma inductively in a process chamber leverages a radial coil network. In some embodiments, the radial coil network is a planar structure comprising an inner conductor with an open center where at least one RF power source is electrically connected to the inner conductor at a power node, an outer conductor spaced away from and surrounding the inner conductor where at least one ground is electrically connected to the outer conductor at a ground node, a plurality of branch conductors extending from the inner conductor to the outer conductor where the plurality of branch conductors is distributed uniformly in the radial coil network, and a plurality of capacitors where at least one capacitor of the plurality of capacitors is electrically interposed into each branch conductor of the plurality of branch conductors.

Inductively coupled plasma source with radial coil network

Certain aspects of the present disclosure provide techniques for slot aggregation in new radio (NR) systems. A method of wireless communication by a user equipment (UE) includes receiving radio resource control (RRC) signaling providing a semi-static configuration for transmission and/or reception of a repeated transport block (TB) and/or a different TB in each of a plurality of aggregated slots. The UE transmits or receives the TBs in the plurality of aggregated slots based on the semi-static configuration. Another method is provided in which the UE transmits and/or receives a demodulation reference signal (DMRS) in each of a plurality of aggregated slots, each DMRS associated with a repeated TB or a different TB in the slot. The UE determines, based on received signaling, whether the DMRS use a same precoder or a different precoder and modulates and/or demodulates the TBs in the plurality of aggregated slots based on the determination.

Signaling for slot aggregation

A semiconductor processing system may include a semiconductor processing chamber configured to execute a recipe on a semiconductor wafer. The system may include a first plasma source to provide plasma to the semiconductor processing chamber and to be duty cycled during an execution of the recipe. The system may also include a second plasma source configured to maintain the plasma in the semiconductor processing chamber while the first plasma source is duty cycled.

Auxiliary plasma source for robust ignition and restrikes in a plasma chamber

Aspects described herein provide a method of performing phase selective convolution, including: receiving multi-phase pre-activation activation data; partitioning the multi-phase pre-activation data; applying a first activation function to the set of first phase pre-activation data to form a set of first phase activation output; convolving the set of first phase activation output with a first convolution kernel to form a first phase output feature map; negating the set of second phase activation data; applying a second activation function to the negated set of second phase pre-activation data to form a set of second phase activation output; convolving the set of second phase activation output with a second convolution kernel to form a second phase output feature map; negating the second phase output feature map; and training the neural network based on the first phase output feature map and the second phase output feature map.

Phase selective convolution with dynamic weight selection

Embodiments provided herein generally include apparatus, plasma processing systems and methods for controlling ion energy distribution in a processing chamber. One embodiment of the present disclosure is directed to a method for plasma processing. The method generally includes: determining a voltage and/or power associated with a bias signal to be applied to a first electrode of a processing chamber, the voltage being determined based on a pressure inside a processing region of the processing chamber such that the voltage is insufficient to generate a plasma inside the chamber by application of the voltage and/or power to the first electrode; applying the first bias signal in accordance with the determined voltage and/or power to the first electrode; and applying a second bias signal to a second electrode of the processing chamber, wherein the second bias signal is configured to generate a plasma in the processing region and the first bias is applied while the second bias is applied.

Ion energy control on electrodes in a plasma reactor

Various implementations disclosed herein include devices, systems, and methods that generate floorplans and measurements using a three-dimensional (3D) representation of a physical environment generated based on sensor data.

Floorplan generation based on room scanning

Embodiments provided herein generally include apparatus, e.g., plasma processing systems, and methods for the plasma processing of a substrate in a processing chamber. Some embodiments are directed to a waveform generator. The waveform generator generally includes a first voltage stage having: a first voltage source; a first switch; a ground reference; a transformer having a first transformer ratio, the first transformer comprising: a primary winding coupled to the first voltage source and the ground reference; and a secondary winding having a first end and a second end, wherein the first end is coupled to the ground reference, and the second end is configured to be coupled to a load through a common node; and a first diode coupled in parallel with the primary winding of the first transformer. The waveform generator generally also includes one or more additional voltage stages coupled to a load through the common node.

Pulsed voltage source for plasma processing applications

Embodiments provided herein generally include apparatus, plasma processing systems and methods for generation of a waveform for plasma processing of a substrate in a processing chamber. One embodiment includes a waveform generator having a voltage source selectively coupled to an output node, where the output node is configured to be coupled to an electrode disposed within a processing chamber, and where the output node is selectively coupled to a ground node. The waveform generator may also include a radio frequency (RF) signal generator, and a first filter coupled between the RF signal generator and the output node.

Plasma excitation with ion energy control

Embodiments of substrate supports for use in substrate processing chambers are provided herein. In some embodiments, a substrate support for use in a substrate processing chamber includes: a pedestal having a first side configured to support a substrate and a second side opposite the first side; a plurality of substrate lift pins extending through the pedestal, wherein a plurality of first gaps are disposed between the plurality of substrate lift pins and respective ones of a plurality of substrate lift pin openings in the pedestal; and vacuum lines that extend from the plurality of substrate lift pin openings and that are configured to pump down the plurality of substrate lift pin openings.

Substrate support gap pumping to prevent glow discharge and light-up

Embodiments of the disclosure provided herein include an apparatus and method for processing a substrate in a plasma processing system. The apparatus includes a pulse voltage (PV) waveform generator comprising at least one synchronization signal and a plurality of pulsers to provide a plurality of TTL inputs. The PV waveform generator generates a waveform containing pulses or bursts which contain micropulses corresponding to the plurality of TTL input signals and the at least one synchronization signal. The method includes receiving a first TTL input signal and a synchronization waveform signal from a controller, delivering a first micropulse to an electrode assembly after receiving the first TTL input signal and synchronization signal, and delivering a second micropulse to the electrode assembly after receiving the second TTL input signal and the synchronization signal.

System and methods for implementing a micro pulsing scheme using dual independent pulsers

Growing community of inventors

San Diego, CA, United States of America

Yang Yang