Innophase Inc.

Qualcomm Incorporated

Carnegie Mellon University

Parallel Wireless, Inc.

Leland Stanford Junior University

Yang Xu

Sara Munoz Hermoso

Nicolo Testi

Roc Berenguer Perez

Per Konradsson

Xuejun Zhang

Xi Li

Timothy Paul Pals

Fa Dai

Dongyi Liao

Jeffrey Shamblin

Steven Paul Papa

Lawrence Thomas Pileggi

Kevin Hsi Huai Wang

Claudio Anzil

Jongheon Kim

Prasad S Gudem

Kevin Hsi-Huai Wang

Xin Liang Li

Stephen P Boyd

Gang Zhang

Solti Peng

Peng Li

Yuanwei Jin

Mehdi Asheghi

Yaniv Kaver

Jian Cui

Jun Pan

Lawrence Piileggi

Farhad Zarkeshvari

Fa Foster Dai

Multi-level beamforming signal processing of frequency-domain inphase and quadrature data packets by a group of serially-connected transceivers. Packets intended for transmission during some frames are formatted according to subarray-level beamforming, while packets for transmission in other frames are formatted according to a full-dimensional level of beamforming.

Transceiver arrays for processing multi-resolution beam-formed data

Transceiver array synchronization by receiving a clock signal and at least one synchronization pulse signal at each transceiver IC of a plurality of transceiver integrated circuit (IC) subarrays, wherein each transceiver IC subarray contains a respective set of serially connected transceiver ICs; and synchronizing the transceiver IC with other transceiver ICs of the respective set of serially connected transceiver ICs by resetting a delta-sigma modulator (DSM) circuit to a predetermined state in accordance with the received at least one synchronization pulse signal.

Integrated circuit transceiver array synchronization

A dual-band, tri-band, or higher-order multi-band array of antenna elements, with each element, or subsets of elements, connected to multiple radios at each antenna port. In one embodiment, an array comprises a 128 element Massive MIMO array having 64 horizontally-polarized (H-pol) and 64 vertically-polarized (V-pol) elements configured to provide dual polarization capability over multiple bands to accommodate highly-configurable simultaneous 4G and 5G operation.

Multi-band massive MIMO antenna array

Transceiver integrated circuit suitable for distributed placement across an active antenna unit. ICs with two serial data ports configured to transmit and receive aggregated signal-port IQ data packets with adjacent ICs within a subarray of ICs, or to a beamformer processor. A packet header inspection circuit may identify aggregated signal-port IQ data packets for local processing, and identify received aggregated signal-port IQ data packets for processing by another device.

Transceiver device for array signal processing

A configurable array having a plurality of antenna elements arranged in at least four adjacent groups of array elements on a panel array, the first group of elements having an inter-element spacing based on a transmit signal wavelength, a second group of elements having an inter-element spacing based on a receive signal wavelength, and a third and fourth group of elements having an inter-element spacing based on a wavelength between the transmit signal wavelength and the receive signal wavelength.

Reconfigurable phase array

Methods disclosed herein may include configuring a plurality of transceiver modules in an antenna array with assigned receive signal weighting factors, the transceiver modules interconnected with high-speed data communication buses, and each transceiver module positioned adjacent to a respective antenna element in the antenna array; configuring the plurality of transceiver modules into inter-communicating module groups by enabling the associated high-speed data communication buses; receiving a plurality of wireless data signals with the plurality of transceiver modules and responsively generating a corresponding plurality of receive baseband data signals; generating a plurality of received beamformed signals by combining subsets of the receive baseband signals within each module group using the assigned receive signal weighting factors by transmitting the receive baseband signals between the transceiver modules within the module group; and demodulating the received beamformed signals.

System and method for massive MIMO communication

Selectively enabling an amplitude processing circuit and a phase processing circuit of a wireless station's polar receiver with respect to reception of a beacon signal. Such systems and methods may include sequentially demodulating symbols of the received beacon signal using at least the phase processing circuit to detect a traffic indication signal value in a data payload portion of the received beacon signal. Upon detecting a condition indicating no data traffic for the wireless station, the phase processing circuit may be turned off. The polar receiver may demodulate symbols of the received beacon signal and upon detecting a beacon preamble symbol sequence, shut off the amplitude processing circuit and set the amplitude to a fixed value. The phase processing circuit in conjunction with the fixed amplitude value may be used to demodulate symbols of the beacon signal.

System and method for low-power wireless beacon monitor

A microcomponent massive MIMO array is presented. The microcomponent massive array includes a general purpose processor and an integrated power amplifier and transmitter device including a software defined radio (SDR) and a plurality of polar power amplifiers (PAs) disposed on a single integrated circuit, wherein the integrated power amplifier and transmitter device is in communication with the general purpose processor. The microcomponent massive MIMO array further includes an antenna array in communication with the integrated power amplifier and transmitter device.

Microcomponent massive MIMO arrays

An example method in accordance with some embodiments includes: determining an output frequency control word (FCW) having a plurality of bits, the output FCW being configured to control an oscillator, the oscillator including a plurality of capacitor banks, the plurality of capacitor banks respectively corresponding to the plurality of bits of the output FCW; storing the output FCW in a clocked delay cell; providing an input clock to the clocked delay cell, wherein the input clock is provided to delay the output FCW by an amount of delay; and, in accordance with the input clock, releasing the delayed output FCW from the clocked delay cell, and respectively applying the plurality of bits of the delayed output FCW to the plurality of capacitor banks of the oscillator.

Phase modulator having fractional sample interval timing skew for frequency control input

An example method according to some embodiments includes receiving, from a modulator, a phase-modulated carrier output signal having a carrier center frequency that is a non-integer multiple of a desired carrier center frequency; generating, by an injection-locked ring oscillator (ILRO), a plurality of phases of the phase-modulated carrier output signal at a plurality of outputs of the ILRO; generating a decoupled fractional frequency output signal by sequentially selecting, using a multiplexer, successive outputs of the plurality of outputs corresponding to successive phases of the plurality of phases, the decoupled fractional frequency output signal having a center frequency equal to an integer multiple of the desired carrier center frequency; and generating, based on the decoupled fractional frequency output signal, a desired phase-modulated carrier output signal that is decoupled from the modulator, the desired phase-modulated carrier output signal having a generated carrier center frequency equal to the desired carrier center frequency.

System and method for dividing the carrier center frequency of an rf modulated signal by a non-integer divisor

A low noise amplifier includes at least two variable gain amplifier stages, each variable gain amplifier configured to accept an input signal and to provide a load driving signal; a tunable bandpass filter connected as a load to each variable gain amplifier stage, wherein each bandpass filter includes a resonant tank, each resonant tank including an inductor, wherein each inductor of each resonant tank is oriented in orthogonal relation with respect to each respective longitudinal axis of each next inductor, the orthogonal relation of the respective longitudinal axes configured to reduce mutual coupling between the tunable bandpass filters; a cross-coupled transistor pair, and at least one cross-coupled compensation transistor pair biased in a subthreshold region configured to add a transconductance component as a function of a load driving signal; and, a controller circuit configured to tune each tunable bandpass filter.

Multi-stage LNA with reduced mutual coupling

A method and circuit for linearizing a frequency response of an oscillator controlled by a plurality of capacitor banks are disclosed. In the disclosed method, for each capacitor bank of at least two capacitor banks of the oscillator, a respective sensitivity characteristic of the capacitor bank is determined. Further, a set of reference output frequency control words (FCWs) for an associated set of frequencies of the oscillator are determined. When an input FCW is received and an output FCW is responsively provided based on (i) an interpolation between two reference output FCWs of the set of reference output FCWs and (ii) the respective sensitivity characteristics of the at least two capacitor banks of the oscillator. The output FCW is then applied to the at least two capacitor banks of the oscillator.

Frequency control word linearization for an oscillator

A polar transmitter including a digital power amplifier cell that includes a first circuit and an amplifier circuit. The first circuit is configured to receive a phase modulated carrier signal and to generate a PMOS control signal and an NMOS control signal such that the PMOS control signal and the NMOS control signal have different duty cycles. The amplifier circuit is configured to receive the PMOS control signal at a PMOS transistor and the NMOS control signal at an NMOS transistor. The first circuit is configured to align the PMOS control signal and the NMOS control signal with respect to one another such that a time that the NMOS transistor and the PMOS transistor of the amplifier circuit are simultaneously conducting is minimized. The amplifier circuit is configured to generate an amplified modulated carrier signal in response to the PMOS and NMOS control signals.

Systems and methods for maximizing power efficiency of a digital power amplifier in a polar transmitter

Wideband polar receivers and method of operation are described. A phase-modulated input signal is received at a polar receiver that includes an injection-locked oscillator. The injection-locked oscillator includes a plurality of injection points. Based on the frequency of the input signal, a particular Nth harmonic is selected, and the input signal is injected at the set of injection points corresponding to the selected Nth harmonic. The injection-locked oscillator generates an oscillator output signal, and the phase of the input signal is determined from the phase of the oscillator output signal. In some embodiments, the oscillator output signal is frequency-multiplied by N, mixed with the input signal, and filtered for use in amplitude detection. The input signal is decoded based on the phase and amplitude information.

Growing community of inventors

Chicago, IL, United States of America

Yang Xu