Motorola Corporation

Yang Wang

Jenn-Hwa Huang

Kurt W Eisenbeiser

William J Ooms

Ellen Lan

Jerald A Hallmark

Daniel S Marshall

Vijay K Nair

Majid M Hashemi

A method of fabricating a field effect transistor including doping a continuous blanket layer in a semiconductor substrate structure adjacent the surface to include a source area and a drain area spaced from the source area. A high dielectric constant insulator layer is positioned on the surface of the semiconductor substrate structure overlying the continuous blanket layer to define a gate area between the source and drain areas. A gate contact on the insulator layer is selected to provide a work function difference that depletes the doped layer beneath the insulator layer. Further, the doped layer depth and dosage are designed such that the doped layer is depleted beneath the insulator layer by the selected work function difference of the gate contact and the semiconductor substrate.

Method and apparatus for creating a voltage threshold in a FET

An electrode structure for semiconductor devices includes first electrode material positioned in overlying relationship to the surface of a substrate so as to define a first side wall perpendicular thereto. A nonconductive side wall spacer is formed on the first side wall and defines a second side wall parallel to and spaced from the first side wall. Second electrode material is formed in overlying relationship to the substrate and on the second side wall so as to define a third side wall parallel to and spaced from the second side wall. The first and second electrode materials are connected as first and second electrodes in a common semiconductor device. Additional electrodes can be formed by forming electrode material on additional side walls.

Electrode structure for transistors, non-volatile memories and the like

A vertical FET is fabricated by etching through a contact layer into a drift layer on a compound semiconductor substrate to form a plurality of mesas, each mesa having an upper surface and each adjacent pair of mesas defining therebetween a trench with sidewalls and a bottom. A conductive layer is conformally deposited over the plurality of mesas and the trenches and anisotropically etched to form contacts on the sidewalls of the trenches and depositing source contacts on the upper surfaces of the mesas and a drain contact on a reverse side of the substrate.

Method of fabricating vertical FET with sidewall gate electrode

A multi-state non-volatile ferroelectric memory includes a field effect transistor having a gate insulator formed of ferroelectric material. The ferroelectric material is separated into regions of different characteristics, e.g. different thicknesses, different coercive field values, etc., so as to provide a plurality of different threshold voltages for the field effect transistor.

Non-volatile multistate memory cell using a ferroelectric gate fet

A semiconductor device includes a buffer layer (23) having a doped region (24), a barrier layer (26) over the buffer layer (23) and having a doped region (27), and a channel layer (25) located between the buffer layer (23) and the barrier layer (26) where the doping density of the doped region (27) in the barrier layer (26) is higher than the doping densities of the channel layer (25) and the doped region (24) in the first buffer layer (23).

Semiconductor device

A high power heterojunction field effect transistor comprising a first barrier layer including a semiconductor material having a band gap, a second barrier layer including a semiconductor material having a band gap, a channel layer including a semiconductor material having a band gap narrower than the band gaps of the material included in the first barrier layer and the second barrier layer and sandwiched therebetween and an interface layer sandwiched between the channel layer and the first barrier layer.

Growing community of inventors

Phoenix, AZ, United States of America

Yang Wang