Taiwan Semiconductor Manufacturing Comp. Ltd.

Yang-Syu Lin

Yu-Hao Hsu

Cheng-Hung Lee

Wei-Jer Hsieh

Chia-Chen Kuo

Che-Ju Yeh

Hua-Hsin Yu

Chi-Ting Cheng

A power management circuit suitable for a memory device and a memory device is provided. The power management circuit includes a first logic circuit, a second logic circuit, and a transmission gate. The first logic circuit is configured to receive an inverted first input signal and a second input signal and generates a first output signal. The second logic circuit is configured to receive a first input signal and the second input signal and generates a second output signal. The transmission gate is configured to receive the first output signal and generates a control signal to at least one power transistor coupled between the power management circuit and the memory device. During a standby mode, the power transistor is turned on to make a first voltage equal to a predetermined voltage and during a sleep mode, the control signal is coupled to a first voltage. The predetermined voltage is greater than the first voltage.

Power management circuit in memory device

Growing community of inventors

Taipei, Taiwan

Yang-Syu Lin