Samsung Electronics Co., Ltd.

Yang-Soo Son

Soon-Moon Jung

Won-Seok Cho

Young-Chul Jang

Jae-Hoon Jang

Min-Sung Song

Young-Seop Rah

Han-Soo Kim

Hyun-Jo Kim

Young-Soo Yoon

Jong-Hyuk Kim

Min-Kwon Choi

Han-Ii Yu

A moisture blocking structure includes an active fin disposed on a sealing region of a substrate, the substrate including a chip region and the sealing region surrounding a periphery of the chip region, the active fin continuously surrounding the chip region and having a winding line shape in a plan view. A gate structure covers the active fin and surrounds the periphery of the chip region. A conductive structure is disposed on the gate structure, the conductive structure surrounding the periphery of the chip region.

Moisture blocking structure and/or a guard ring, a semiconductor device including the same, and a method of manufacturing the same

A semiconductor device includes a semiconductor substrate including a first region having a cell region and a second region having a peripheral circuit region, first transistors on the semiconductor substrate, a first protective layer covering the first transistors, a first insulation layer on the first protective layer, a semiconductor pattern on the first insulation layer in the first region, second transistors on the semiconductor pattern, a second protective layer covering the second transistors, the second protective layer having a thickness greater than that of the first protective layer, and a second insulation layer on the second protective layer and the first insulation layer of the second region.

Method for forming semiconductor device having metallization comprising select lines, bit lines and word lines

On embodiment of a contact structure may include a lower insulation layer on a lower substrate, an upper substrate on the lower insulation layer, a groove penetrating the upper substrate to extend into the lower insulation layer, the groove below an interface between the upper substrate and the lower insulation layer, an upper insulation layer in the groove, and a contact plug penetrating the upper insulation layer in the groove to extend into the lower insulation layer.

Contact structures in substrate having bonded interface, semiconductor device including the same, methods of fabricating the same

A NAND flash memory device includes a lower semiconductor layer and an upper semiconductor layer located over the lower semiconductor layer, a first drain region and a first source region located in the lower semiconductor layer, and a second drain region and a second source region located in the upper semiconductor layer. A first gate structure is located on the lower semiconductor layer, and a second gate structure is located on the upper semiconductor layer. A bit line is located over the upper semiconductor layer, and at least one bit line plug is connected between the bit line and the first drain region, where the at least one bit line plug extends through a drain throughhole located in the upper semiconductor layer.

NAND flash memory devices having 3-dimensionally arranged memory cells and methods of fabricating the same

Semiconductor memory device having metallization comprising select lines, bit lines and word lines

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Yongin-si, South Korea

Yang-Soo Son