Synopsys, Inc.

Yang-Ming Chen

Hsiang-Wen Chang

Youxin Gao

Mu-Shun Lee

A method and system for guided power grid augmentation determines a minimum resistance path for cells within an integrated circuit (IC) design. The minimum resistance path traces a conducting wire connecting a pin of a cell to an IC tap within the IC design. A voltage drop value for each of the cells is determined so as to identify target cells having a voltage drop value that satisfies a voltage drop criteria. Polygons have defined size characteristics are defined around the minimum resistance paths of the target cells, and conductors, such as additional conductors, are generated within the defined polygons.

Guided power grid augmentation system and method

A system is disclosed that includes a memory and a processor to perform operations, including analyzing rail voltage drop for a full-chip to identify an IR drop violation in a block design of the full-chip. The operations include performing a block-level rail voltage drop analysis for the block design and generating a revised block design corresponding to the block design in which the IR drop violation is identified. The operations include performing a block-level rail voltage drop analysis on the revised block design to verify that the IR drop violation is fixed and integrating the revised block design into the full-chip to replace the block design upon verifying that the IR drop violation is fixed. The operations include performing the rail voltage drop analysis for the full-chip comprising the revised block design.

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Taipei, Taiwan

Yang-Ming Chen