Micron Technology Incorporated

Yang Lu

Kang-Yong Kim

Hyun Yoo Lee

John Christopher Sancon

Sujeet V Ayyapureddi

Markus H Geiger

Edmund Gieske

Mark K Hadrick

Danilo Caraccio

Ameen D Akel

Nathaniel J Meier

Amitava Majumdar

Cagdas Dirik

Robert Michael Walker

Christopher Heaton Stoddard

Zhenming Zhou

Jiangli Zhu

Tingjun Xie

Qing Liang

Elliott Clifford Cooper-Balis

Francesco Douglas Verna-Ketel

Yu-Sheng Hsu

Smruti Subhash Jhaveri

Elliott C Cooper-balis

Creston M Dupree

Yuan He

Marco Sforzin

Paolo Amato

Hyunyoo Lee

Keun Soo Song

Xinyu Wu

Wonjun Choi

Erik T Barmon

Ke Wei Chan

Niccolo′ Izzo

Niccolo Izzo

Apparatuses and techniques for implementing a data sense amplifier circuit with a hybrid architecture. With the hybrid architecture, the data sense amplifier circuit includes a first set of amplifiers that are shared by multiple banks and includes a second set of amplifiers with multiple subsets dedicated to different banks. The bank-shared amplifiers support memory operations (e.g., a read operation) across multiple banks. Each amplifier within the first set of amplifiers is coupled to at least two banks. The bank-specific amplifiers support usage-based disturbance mitigation for a corresponding bank. Each amplifier within the second set of amplifiers is coupled to one of the multiple banks. The bank-shared amplifiers enable the data sense amplifier circuit to have a smaller footprint while the bank-specific amplifiers enable the data sense amplifier circuit to support usage-based disturbance mitigation and avoid conflicts associated with some sequences of commands.

Data sense amplifier circuit with a hybrid architecture

Described apparatuses and methods provide adaptive selection of a configuration-dependent operand. Adaptive selection enables a die to automatically detect its configuration and dynamically read from or write to configuration-dependent operands of one or more mode registers based on the configuration. In this manner, a memory device with dies having a first byte width (e.g., 1 byte) can be transparent to a memory channel having a second byte width that is larger than the first byte width (e.g., two bytes). For example, two 8-bit dies enabled with aspects of adaptive selection may be coupled to a 16-bit memory channel and each automatically detect its byte position (e.g., upper byte or lower byte). Based on the detected byte position or byte indicator, the 8-bit dies may be configured for use through respective mode registers that correspond to the byte position or assignment of the die.

Adaptive selection of a configuration-dependent operand

A dynamic random access memory employs either or both of a normal row copy operation or a fast row copy operation to copy selected data from a first row of memory to a second row of memory, without transferring the data to an intermediary processor such as a central processing unit or a memory controller. Both operations depend on a concurrent electrical activation of two separate wordlines within a bank of a DRAM. For the fast row copy operation, the two separate wordlines are part of a shared section of a DRAM bank, having shared bitlines. Bit values are copied directly in parallel via common bitlines. For the normal row copy operation, the two separate wordlines are part of a common bank but not a shared section. Bit values are copied in serial via a general input/output bus within the bank.

DRAM row copy

This disclosure describes aspects of memory die interconnections to physical layer interfaces (PHYs) that may enable expanded channel bus width and improved signal integrity (SI). In aspects, a memory die is operably coupled to a first PHY via a command-and-address (CA) bus and data input/output (DQ) bus of the first PHY and to a second PHY via a chip select (CS) bus of the second PHY. The second PHY may provide a CS signal to the memory die, and the first PHY can perform a training procedure via CA signaling or DQ signaling. The training procedure may improve SI between the memory die and the PHYs. Additionally, a memory die may be interconnected to different PHYs to expand a channel bus width. Thus, by interconnecting memory dies to one or more PHYs as described herein, improved SI and expanded channel bus width can be achieved.

Memory die interconnections to physical layer interfaces

Described apparatuses and methods relate to a bank-level self-refresh for a memory system. A memory device can include a controller with logic that implements self-refresh operations in the memory device. The logic may perform self-refresh operations on a set of banks of the memory device that is less than all banks within the memory device. The set of banks of the memory device may be determined such that the peak current in a power distribution network of the memory device is bounded when the self-refresh operation is performed. Accordingly, bank-level self-refresh can reduce a cost of the memory device of a memory system by enabling use of a less complicated power distribution network. The bank-level self-refresh may also be implemented with different types of refresh operations. Amongst other scenarios, bank-level self-refresh can be deployed in memory-expansion environments.

Bank-level self-refresh

This document describes apparatuses and techniques for die-based rank management for a memory system. In various aspects, a die-based rank controller (controller) can determine which memory dies of a memory device are not functional to store data and correlate rank selections of a memory system to ranks of other memory dies (e.g., functional memory dies). The controller may store information that indicates the correlation or mapping of the rank selections to the ranks of the other memory dies to enable access to those ranks of the memory system. In some aspects, the controller receives a command to access the memory device with a rank selection, and the controller enables access to a corresponding rank based on the information. By so doing, aspects of die-based rank management enable memory packages with non-functional memory dies to be used instead of discarded, which can increase production utilization or lower manufacturing costs.

Die-based rank management

Described apparatuses and methods relate to adaptive wordline refresh for a memory system that may support a nondeterministic protocol. To help manage power delivery networks in a memory system, a memory device can include logic that can stagger activation of multiple wordlines that are to be activated or refreshed approximately simultaneously. The logic circuitry can be coupled between wordlines that are to be activated and delay propagation of the activation signal. Thus, a first group of wordlines (e.g., 'before' the logic circuitry) are activated by the signal, but activation of a second group of wordlines (e.g., “after” the logic circuitry), is delayed, reducing the peak current draw. Additional logic circuitries can be coupled between the wordlines to divide the wordlines into multiple groups, thereby staggering the activation of wordlines that are activated by a refresh command, which can reduce the peak current draw and power consumption.

Adaptive wordline refresh

Described apparatuses and methods enable a system including at least one memory device to load different address scramble patterns on dies of the memory device. The address scramble patterns may include the logical-to-physical conversion of rows in the memory device or the memory dies. In aspects, the apparatuses and methods can change the address scrambles at different intervals, such as after a power reset or when the data stored on the memory device is invalid, not current, flushable, or erasable. The described aspects may reduce effectiveness of usage-based disturb attacks used by malicious actors to discover a layout of a type of particular memory device or memory die.

Dynamic address scramble

There are provided systems and methods that include at least one memory that has a plurality of memory cells. The cells may be disposed in rows and columns. The device can further include a controller that is communicatively coupled to the at least one memory, and the controller may be configured by its hardware topology and its instruction set and/or by a communicatively coupled processor or higher-level system or subsystem to maintain data integrity in the at least one memory and/or to prevent or mitigate malicious access patterns that may compromise the at least one memory. The controller may be configured to execute a deterministic protocol in conjunction with or sequentially to a probabilistic protocol to achieve one or more of the above-noted functions.

Row access strobe (RAS) clobber and row hammer failure mitigation

In various examples, refreshing a bank can include receiving a refresh command, wherein the refresh command comprises selector bits and receiving mode register bits from the mode registers. Refreshing a bank can also include refreshing a number of banks from the plurality of banks utilizing the mode register bits and the selector bits.

Bank selection for refreshing

Described apparatuses and methods relate to a bank-level self-refresh for a memory system. A memory device can include logic that implements self-refresh operations in the memory device. The logic may perform self-refresh operations on a set of banks of the memory device that is less than all banks within the memory device. The set of banks of the memory device may be determined such that the peak current in a power distribution network of the memory device is bounded when the self-refresh operation is performed. Accordingly, bank-level self-refresh can reduce a cost of the memory device of a memory system by enabling use of a less complicated power distribution network. The bank-level self-refresh may also be implemented with different types of refresh operations. Amongst other scenarios, bank-level self-refresh can be deployed in memory-expansion environments.

Described apparatuses and methods relate to selectively disabling a die that may be included in a multiple-die package without necessarily disabling all the remaining dies within the package. A nonvolatile circuit, such as one or more fuses, may be included within individual dies and/or otherwise incorporated within the package. The nonvolatile circuit maintains a value for the die that is indicative of the operability of the die. Die disablement logic is operatively coupled to the nonvolatile circuit and can disable the die based on the value indicating that the die is unusable. The disabling of the die by the die disablement logic may be controlled by an override signal that allows the disabling or prevents the logic from disabling the die. Thus, the die disablement logic can prevent a defective die from functioning, but the die disablement logic may be overridden for testing or debugging.

Die disablement

There are provided systems and methods that include at least one memory that has a plurality of memory cells. The cells may be disposed in rows and columns. The device can further include a controller that is communicatively coupled to the at least one memory, and the controller may be configured by its hardware topology and its instruction set and/or by a communicatively coupled processor or higher level system or subsystem to maintain data integrity in the at least one memory and/or to prevent or mitigate malicious access patterns that may compromise the at least one memory. The controller may be configured to execute a deterministic protocol in conjunction with or sequentially to a probabilistic protocol to achieve one or more of the above-noted functions.

Row access strobe (RAS) clobber and row hammer failures using a deterministic protocol

An apparatus can include memory devices and a memory controller coupled to the memory devices via memory channels. The memory channels can disable a first memory channel associated with a first memory die in a respective memory chip of a memory device and perform a memory operation via a second memory channel involving a second memory die in the respective memory chip.

Memory channel disablement

Described apparatuses and methods facilitate bus training with multiple dice, such as multiple memory dice. A controller can communicate with multiple dice over a bus to perform bus training by sending a test pattern and receiving in return a feedback pattern indicative of the bits detected by the dice. Because suitable signal timing can differ between dice, even those using the same bus, the controller may attempt to train each die separately from the others. In some situations, however, individualized training may be infeasible. To accommodate such situations, logic associated with two or more dice can combine the bits as detected from the test pattern into a combined feedback pattern. A timing parameter that is jointly suitable for multiple dice can be determined, and the bus training may be concluded, responsive to the combined feedback pattern matching the test pattern. The multiple dice may be stacked or linked.

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Boise, ID, United States of America

Yang Lu