United Microelectronics Corp.

Yang-Ling Wu

Chung-Yuan Lee

Chun-Liang Hu

Shih-Hsiung Chiu

Chih-Yung Kang

A memory circuit, including multiple storage cells arranged in an array with multiple columns and rows, multiple word lines extending in row direction and connecting with the gates of storage cells, multiple bit lines extending in column direction and connecting respectively with the storage cells, wherein the storage cells in each row correspond to m word lines, m is an integer equal or greater than 2, and the m word lines are sequentially and alternately connected with the storage cells in the row. Alternatively, the storage cells of each column correspond to n bit line, n is an integer equal or greater than 2, and the n bit lines are sequentially and alternately connected with the storage cells in the column.

Memory circuit

A trim circuit for an e-fuse unit includes: a mirroring circuit for receiving an enable signal, when triggered by the enable signal, the mirroring circuit generating a driving voltage; and a driving transistor coupled to the mirroring circuit, in response to the driving voltage from the mirroring circuit, the driving transistor turning ON to generate a MOS current to an output node, wherein the output node is coupled to the e-fuse unit, and in response to the MOS current from the output node, the e-fuse unit is burned out.

Growing community of inventors

Taichung, Taiwan

Yang-Ling Wu