Intel Corporation

Yang Liang Poh

Bok Eng Cheah

Jackson Chung Peng Kong

Kooi Chi Ooi

Jenny Shio Yin Ong

Seok Ling Lim

Yean Ling Soon

Ling Li Ong

Kin Wai Lee

The present disclosure is directed to semiconductor packages, and methods for making them, which includes a substrate with a top surface and a bottom surface, a substrate recess in the bottom surface of the substrate, a first device positioned over the top surface of the substrate, which has the first device at least partially overlapping the substrate recess, a mold material in the substrate recess, which has the mold material overlapping the bottom surface of the substrate adjacent to the substrate recess, a second device positioned in the substrate recess, and a plurality of interconnect vias in the substrate, which has at least one of the plurality interconnect vias coupled to the first and second devices to provide a direct signal connection therebetween that minimizes signal latency.

Multi-chip package with recessed memory

A semiconductor package substrate includes an encapsulated interconnect on a land side of the substrate. The encapsulated interconnect includes an integral metallic structure that has a smaller contact end against the semiconductor package substrate, and a larger contact end for board mounting.

Encapsulated vertical interconnects for high-speed applications and methods of assembling same

The present disclosure relates to a semiconductor package that may include a substrate. The substrate may have a top surface and a bottom surface. The semiconductor package may include an opening in the substrate. The semiconductor package may include a bridge disposed in the opening. The bridge may have an upper end at the top surface of the substrate and a lower end at the bottom surface of the substrate. The semiconductor package may include a first die on the top surface of the substrate at least partially extending over a first portion of the upper end of the bridge. The semiconductor package may include a second die on the bottom surface of the substrate at least partially extending over the lower end of the bridge. The bridge may couple the first die to the second die.

Vertical die-to-die interconnects bridge

An electronic device and associated methods are disclosed. In one example, the electronic device can include an assembly having asymmetrically situated conductors. In selected examples, the assembly includes a ground plane, a central shield portion, a first side shield portion on a first side, a second side shield portion on a second side, a first conductor asymmetrically situated between the central shield portion and the first side shield portion, a second conductor asymmetrically situated between the central shield portion and the second side shield portion, and dielectric within the assembly.

Growing community of inventors

Penang, Malaysia

Yang Liang Poh