University of California

Yang-Kyu Choi

Jeffrey Bokor

Chenming Hu

Leland Chang

Wen-Chin Lee

Vivek Subramanian

Tsu-Jae King

Ji Zhu

Gabor A Somorjai

Jeff Grunes

Nick Lindert

Jakub Tadeusz Kedzierski

Xuejue Huang

Fabrication methods disclosed herein provide for a nanoscale structure or a pattern comprising a plurality of nanostructures of specific predetermined position, shape and composition, including nanostructure arrays having large area at high throughput necessary for industrial production. The resultant nanostracture patterns are useful for nanostructure arrays, specifically sensor and catalytic arrays.

Methods for fabrication of positional and compositionally controlled nanostructures on substrate

A FinFET device is fabricated using conventional planar MOSFET technology. The device is fabricated in a silicon layer overlying an insulating layer (e.g., SIMOX) with the device extending from the insulating layer as a fin. Double gates are provided over the sides of the channel to provide enhanced drive current and effectively suppress short channel effects. A plurality of channels can be provided between a source and a drain for increased current capacity. In one embodiment two transistors can be stacked in a fin to provide a CMOS transistor pair having a shared gate.

Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture

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Albany, CA, United States of America

Yang-Kyu Choi