Korea Advanced Institute of Science and Technology

Korea Research Institute of Bioscience and Biotechnology

Lg Chem, Ltd

Korea Institute of Science and Technology

Samsung Electronics Co., Ltd.

Center for Integrated Smart Sensors Foundation

Korea Research Institute of Bioscience

H Bion Co., Ltd.

Yang-Kyu Choi

Tae-Sook Jeong

Myung-Sook Choi

Song-Hae Bok

Chul-Ho Lee

Surk-Sik Moon

Byung-Hwa Hyun

Yong-Kook Kwon

Eun-Sook Lee

Ki-Hwan Bae

Yong-Bok Park

Seong-Tae Kim

Sae-Bom Lee

Jun-Yeob Seong

Young-Bae Park

Hyo-Soo Kim

Sang-Yoon Jeong

Jun-Young Park

Hyuk An

Og-Sung Moon

Kuk-Hwan Kim

Dong-Gun Park

Dong-won Kim

Sung-Young Lee

Woo-Song Lee

Hyoung-Chin Kim

Ju-Ryoung Kim

Jae Hur

Young-Ho Lee

Kwang-Hee Son

Byoung-Mog Kwon

Ju-hyun Kim

Hyun Gyu Park

Young-Kook Kim

Sung-Gyu Kim

Sung-Uk Kim

Jong-Hyuk Park

Kyoung-Ran Im

So-Jin An

Woo-Suk Hwang

Byeong-Chun Lee

Ki-Chang Jang

Jun-Seock Son

Hyunjin Lee

Byung-Hyun Lee

Hyun-Soo Yoon

Byung-Tae Ahn

Myung-Su Kim

Lee-Eun Yu

Tae Won Kim

Ingyu Hwang

Doil Choi

Jung-Ah Ahn

Chang-Hoon Kim

Bo-Sung Kim

Sung-Il Roh

Young-June Ryu

Eu-Gene Lee

Sang-Ku Lee

Soon-Woong Kim

Dae-Kee Kwon

Ja-Min Koo

Min-Ho Kang

Youn-Young Hwang

Ju-Ryong Kim

Jun-Sung Lee

Seong-Choon Choe

Joon-Kyu Han

Jun Woo Son

Chang-Hoon Jeon

Oktay Yarimaga

Dae-Chul Ahn

Yun Kyung Jung

Hyungsoon Im

Bonsang Gu

Joonkyu Han

Hagyoul Bae

Eul-Soon 202-906 Hanyang Apt Park

Sun-Jong 304-1102 Sinsung-Eunhasoo Apt Kim

Sung-Keun 936-807 Faculty Apt Kang

Hee-Sun 935-502 Dormitory Kwon

Shin-Yong Moon

Cu-Rie Ahn

Sun-Kyung Oh

Disclosed is a single transistor with a double gate structure for an adjustable firing threshold voltage and a neuromorphic system using the same. A single transistor neuron with a double gate structure according to an example embodiment includes a barrier material layer formed on a semiconductor substrate and comprising a hole barrier material or an electron barrier material; a floating body layer formed on the barrier material layer; a source and a drain formed at both sides of the floating body layer, respectively; a driving gate formed at a first side of the floating body layer without contacting the source and the drain; a control gate formed at a second side of the floating body layer without contacting the source and the drain; and a gate insulating film formed between the floating body layer and the driving gate and between the floating body layer and the control gate.

Single transistor with double gate structure for adjustable firing threshold voltage, and neuromorphic system using the same

Disclosed are a DRAM device capable of storing charges for a long time and an operating method thereof. According to an embodiment, a DRAM device includes a channel region formed on a substrate, a gate insulating film region formed on the channel region, a floating gate region formed on the gate insulating film region, a transition layer region formed on the floating gate region, and a control gate region formed on the transition layer region and generating a potential difference with the floating gate region in response to a fact that a potential that is not less than a reference potential is applied and releasing at least one charge stored in the floating gate region or storing the at least one charge into the floating gate region, by generating a transition current due to the potential difference.

Dynamic random access memory device with long retention and operating method thereof

A steep-slope field-effect transistor and a fabrication method thereof are disclosed. The steep-slope field-effect transistor according to an embodiment of the inventive concept includes a source, a channel region, and a drain formed on a substrate; a gate insulating film formed on an upper portion of the channel region; a floating gate formed on an upper portion of the gate insulating film; a transition layer formed on an upper portion of the floating gate; and a control gate formed on an upper portion of the transition layer. The steep-slope field-effect transistor applies a reference potential or more to the control gate to discharge or bring in at least one charge stored in the floating gate.

Steep-slope field-effect transistor and fabrication method thereof

A two-terminal biristor in which a polysilicon emitter layer is inserted and a method of manufacturing the same are provided. The method of manufacturing the two-terminal biristor according to an embodiment of the present disclosure includes forming a first semiconductor layer of a first type on a substrate, forming a second semiconductor layer of a second type on the first semiconductor layer, forming a third semiconductor layer of the first type on the second semiconductor layer, and forming a polysilicon layer of the first type on the third semiconductor layer.

Two-terminal biristor with polysilicon emitter layer and method of manufacturing the same

A structure and an operation of a transistor, which is a vertical transistor in which a nanowire-type floating body layer is vertically formed or a horizontal transistor in which a floating body layer is horizontally formed, and implements a spike operation of a neuron by storing and releasing charges inside the transistor, and a neuromorphic system using the same are provided. The vertical transistor includes a floating body layer in a form of a vertical nanowire vertically formed on a substrate, a source and a drain formed above and below the floating body layer, a gate insulating layer formed on the source and surrounding the floating body layer, a gate formed outside the gate insulating layer, and a contact metal being in contact with the source, the drain and the gate to input or output an electrical signal.

Structure and operation method of transistor acting as a neuron in neuromorphic system, and a neuromorphic system using it

A semiconductor channel based neuromorphic synapse deviceincluding a trap-rich layer may be provided that includes: a first to a third semiconductor regions which are formed on a substrate and are sequentially arranged; a word line which is electrically connected to the first semiconductor region; a trap-rich layer which surrounds the second semiconductor region; and a bit line which is electrically connected to the third semiconductor region. When a pulse with positive (+) voltage is applied to the word line, a concentration of electrons emitted from the trap-rich layer to the second semiconductor region increases and a resistance of the second semiconductor region decreases. When a pulse with negative (&#x2212;) voltage is applied to the word line, a concentration of electrons trapped in the trap-rich layer from the second semiconductor region increases and the resistance of the second semiconductor region increases.

Semiconductor channel based neuromorphic synapse device including trap-rich layer

Disclosed is a field effect transistor based on vertically integrated gate-all-around multiple nanowire channels including forming vertically integrated multiple nanowire channels in which a plurality of nanowires is vertically integrated, forming an interlayer dielectric layer (ILD) on the vertically integrated multiple nanowire channels, forming a hole in the interlayer dielectric layer such that at least some of the vertically integrated multiple nanowire channels are exposed, and forming a gate dielectric layer on the interlayer dielectric layer to fill the hole, wherein the forming of the gate dielectric layer on the interlayer dielectric layer to fill the hole includes depositing the gate dielectric layer on the interlayer dielectric layer to surround at least some of the vertically integrated multiple nanowire channels that are exposed though the hole. Nanowires may include various shapes of current channels that have efficient structures for current path. The cross section of the nanowire can be one of a circle shape, squared shape, rectangular shape, round shape, triangular shape, rhombus shape, eclipse shape, and others.

Field effect transistor based on vertically integrated gate-all-round multiple nanowire channels

The present invention provides a thermal hardware-based data security device that is capable of physically, hardware-wise, and permanently erasing data stored in a memory and of enabling a storage device to be reused, and a method thereof. The thermal hardware-based data security device includes: a memory chip capable of storing data; a heater module which supplies heat to permanently erase the data stored in a memory cell within the memory chip; and a switch module which short-circuits the heater module between a power supply unit and a ground when switched on, and thus, controls the heater module to be operated.

Thermal hardware-based data security device that permanently erases data by using local heat generation phenomenon and method thereof

Disclosed are a clamping device and a battery module comprising the same, the clamping device being suitable for reducing the number of screw coupling portions of long bolts at a lower plate, a battery stack, and an upper plate, and for securing, in a balanced manner, the battery stack, the lower plate and the upper plate by means of the long bolts. The clamping device according to the present invention comprises: a support; and pressing parts respectively protruded from one end and the other end of the support, wherein the support and the pressing parts define a bent part along the central portion of the outer circumference while forming a band shape, and the pressing parts include locking holes which intersect with the bent portion.

Clamping device, and battery module comprising same

Disclosed is a method of manufacturing a junctionless transistor based on vertically integrated gate-all-around multiple nanowire channels including forming vertically integrated multiple nanowire channels in which a plurality of nanowires is vertically integrated, forming an interlayer dielectric layer (ILD) on the vertically integrated multiple nanowire channels, forming a hole in the interlayer dielectric layer such that at least some of the vertically integrated multiple nanowire channels is exposed, and forming a gate dielectric layer on the interlayer dielectric layer to fill the hole, wherein the forming of the gate dielectric layer on the interlayer dielectric layer to fill the hole includes depositing the gate dielectric layer on the interlayer dielectric layer to surround at least some of the vertically integrated multiple nanowire channels which is exposed though the hole.

Junctionless transistor based on vertically integrated gate-all-round multiple nanowire channels and method of manufacturing the same

Disclosed are a vertically-integrated 3-dimensional flash memory for improving a reliability of cells and a fabrication method thereof. The fabrication method of the vertically-integrated 3-dimensional flash memory includes sequentially stacking a first insulating layer and a second insulating layer on a substrate to form a plurality of insulating layers, etching a portion of the insulating layers to expose an area of the substrate, forming a channel layer on a side surface of the etched insulating layers and on the substrate, forming a first macaroni layer on the channel layer, and forming a second macaroni layer on the first macaroni layer such that a side surface and a lower surface of the second macaroni layer are surrounded by the first macaroni layer.

Vertically-integrated 3-dimensional flash memory for high reliable flash memory and fabrication method thereof

The present disclosure discloses a battery pack suitable for preventing simultaneous separation of both ends of a handle unit from an upper case during transportation of a lower case and the upper case that are laminated sequentially. The battery pack according to the present disclosure includes the lower case and the upper case stacked sequentially to encase a battery module, wherein the upper case includes a housing and a handle unit relatively rotated with respect to the housing to be seated on the housing, and the handle unit has shaft hooks that are penetrated by the rotation supporting shafts of the housing and that are each rotary-coupled to each of the rotation supporting shafts in different angles.

Battery pack

Provided is a battery module including: a battery cell assembly including a plurality of battery cells stacked with one another; end plates configured to cover front and rear portions of the battery cell assembly and to be coupled to the battery cell assembly at a side of each of the end plates; and a fixing holder configured to be mounted to a battery cell assembly at an opposite side of each of the end plates in order to at least partially cover the battery cell assembly, and to protrude from front and rear portions of the end plates.

Battery module, battery pack including battery module, and automobile including battery pack

Provided is a bus bar structure which may be suitable for reducing an occupied area of a printed circuit board (PCB) by removing a fuse from the PCB in an interconnect board (ICB) assembly of a battery pack. According to the present disclosure, the bus bar structure may include: bus bars which face each other and are arranged below the PCB in the ICB assembly of the battery pack; and a fuse case between the bus bars, wherein the fuse case includes a fuse wire therein and is configured to bring the fuse wire into contact with the bus bars via at least one end thereof.

Bus bar structure with fuse case between bus bars

The present disclosure discloses a pack case suitable for preventing vibration or deviation of a battery module on a case during an assembly operation, and a battery pack including the same. The pack case according to the present disclosure includes an align unit and a bus bar disposed at an edge on an inner circumferential surface, and a main case having a connection terminal contacting the bus bar on an outer circumferential surface, and the align unit and the bus bar contact a battery module at a periphery of the battery module seated on the inner circumferential surface of the main case.

Pack case and battery pack comprising same

Growing community of inventors

Daejeon, South Korea

Yang-Kyu Choi