Samsung Electronics Co., Ltd.

Yang-koo Lee

Kyung-seok Oh

Young-Hoon Park

Dong-Ho Shin

Young-hoon Park

Ki-heum Nam

Chil-kun Pong

Myeon-koo Kang

A CMOS integrated circuit includes an NMOS transistor and a PMOS transistor in an integrated circuit substrate. The NMOS transistor and the PMOS transistor each include a gate, and a source/drain on opposing sides of the gate. An insulating layer is located on the integrated circuit substrate. The insulating layer includes a contact hole therein which exposes a portion of a corresponding one of the source/drains. A source/drain plug is formed in the corresponding one of the source/drains. The source/drain plug is of opposite conductivity from the corresponding one of the source/drains. The source/drain plug is centered about the portion of the corresponding one of the source/drains. The source/drain plug may be formed by ion implantation through the contact hole and is thereby self-aligned to the contact hole. The source/drain plug can compensate for misalignment and the diffusion for highly integrated CMOS devices.

Methods for fabricating CMOS integrated circuits including source/drain compensating regions

A diffusion system for manufacturing semiconductor devices has an air curtain formed across a furnace opening for preventing the loss of heat energy from inside the furnace. The diffusion system includes the furnace having an opening through which a wafer boat having a plurality of wafers is loaded/unloaded; an air curtain apparatus for spraying a gas across the opening so as to form an air curtain cutting off the atmosphere inside of the furnace from the outside environment; and a controlling unit for controlling the air curtain apparatus by applying on/off signals to the air curtain apparatus. The diffusion system is controlled by the controlling unit so as to form the air curtain at the opening of the furnace while the wafer boat moves in and out of the furnace. After the wafer boat is completely loaded into the furnace, the air curtain is removed.

Diffusion system having air curtain formation function for manufacturing semiconductor devices and method of controlling the same

CMOS integrated circuits including source/drain plug

A fabrication method of a semiconductor device is disclosed. Particularly, in the process of forming a gate oxide film on a semiconductor substrate, the method for forming a gate oxide film of a semiconductor device comprises the steps of first-annealing the semiconductor substrate in a nitrogen (N.sub.2) atmosphere; forming a gate oxide film by wet-oxidizing the annealed semiconductor substrate at a low temperature in a mixed gas atmosphere of oxygen (O.sub.2) and hydrogen (H.sub.2); and second-annealing the semiconductor substrate where gate oxide film has been formed, at a high temperature in a nitrogen (N.sub.2) atmosphere. Accordingly, the thinning phenomenon of the gate oxide film near the field oxide film is prevented and the instability such V.sub.FB in the conventional field oxidation method is considerably recovered. Also, the field concentration phenomenon is decreased and tolerance to dielectric breakdown is increased.

Method for forming a gate oxide film of a semiconductor device

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Seoul, South Korea

Yang-koo Lee