Samsung Electronics Co., Ltd.

Hyundai Motor Company

Nanoionics Korea Co., Ltd.

Kia Motors Corporation

Yang-Ki Kim

Jung-Hwan Choi

Ji-Hye Kim

Tae-Won Lee

Sun-Mi Oh

Hyun-Soo Sohn

Jong-Min Kwon

Jun-Bae Kim

Seong-Hwan Jeon

Beom-Yong Kil

Byung-Chul Kim

Young Jae Choi

Seok-Hun Hyun

Jung-Joon Lee

You-Keun Han

Young-Jin Jeon

Sung-joo Park

Chul-Hwan Choo

Seok-Il Kim

Kyoung-Sun Kim

Jea-Eun Lee

Tae-Sik Na

Young-jin Jeon

Ho-Suk Lee

Seok-Woo Choi

Seok-hun Hyun

Jun-ho Shin

Hae-young Chung

An integrated circuit device includes a read strobe signal transmitter including a main output drive circuit and a victim output drive circuit having an output terminal electrically coupled to an output terminal of the main output drive circuit. The read strobe signal transmitter is configured to: (i) generate a periodic active read strobe signal during a read time interval, in response to a pair of periodic drive signals, which are 180&#xb0; out-of-phase relative to each other during the read time interval, and (ii) generate a disabled read strobe signal at a fixed logic level during a non-read time interval, in response to an active victim control signal. The main output drive circuit is responsive to the pair of periodic drive signals during the read time interval, and the victim output drive circuit is responsive to the active victim control signal during the non-read time interval.

Integrated circuit devices having strobe signal transmitters with enhanced drive characteristics

A solid electrolyte COsensor may include a solid electrolyte bonded to a substrate to join and seal the substrate, a sensing electrode formed at a first side of the solid electrolyte, and a reference electrode formed between a second side of the solid electrolyte and one surface of the substrate, and sealed by the solid electrolyte and the substrate.

Solid electrolyte carbon dioxide sensor and manufacturing method thereof

A solid electrolyte-type COsensor having a reduced influence from volatile organic compounds (VOCs), includes: a solid electrolyte; a reference electrode which is formed at one side of the solid electrolyte; a detecting electrode of which one side is joined and which is formed at the other side of the solid electrolyte; a substrate which is formed at the other side of the reference electrode; and an oxidation catalyst which is formed at the other side of the detecting electrode.

Solid electrolyte-type carbon dioxide sensor having reduced influence from volatile organic compounds

A temperature compensation method for a gas sensor module using a change of heater current, may include deriving an output voltage equation of the gas sensor module from a cell reaction equation of an electrolyte and deriving the output voltage equation to an equation for a fluctuation temperature which varies depending on a sensor temperature and an unknown type compensation coefficient; deriving the fluctuation temperature to heater current indicating a current value of a heater formed in the gas sensor module and deriving the output voltage equation by the heater current and the compensation coefficient; and measuring output voltage depending on current of heaters at two or more points to determine the compensation coefficient of the output voltage equation, and the output voltage is configured to be compensated with the change of the heater current measured by the gas sensor module regardless of an external temperature.

Temperature compensation method for gas sensor module using change of heater current

A semiconductor memory device that includes a command decoder, a refresh controller, an oscillator and a delay unit. The command decoder generates a self refresh command, and the oscillator generates an oscillation signal. The refresh controller generates a refresh control signal and a recovery signal in response to the self refresh command and the oscillation signal. The delay unit transitions internal nodes included in the delay unit that are not transitioned during a refresh period in response to the refresh control signal and the recovery signal.

Semiconductor memory device capable of preventing negative bias temperature instability (NBTI) using self refresh information

A clock synchronization circuit includes a delay-locked loop (DLL) and a delay-locked control unit. The DLL is configured to generate an output clock signal by delaying an input clock signal by a delay time, and to execute a delay-locking operation in which the delay time is adjusted to a locked state according to a comparison between the output clock signal and the input clock signal. The delay-locked control unit configured to detect the locked state of the DLL, and to control the DLL based on the determined locked state.

Clock synchronization circuit and semiconductor memory device including clock synchronization circuit

A semiconductor device includes a resistor terminal, a reference voltage generator and a detector. The resistor terminal is connected to an external resistor. The reference voltage generator generates at least one reference voltage. The detector generates a detection signal based at least in part on a resistor terminal voltage and the at least one reference voltage. The detection signal indicates a state of an electrical connection to the resistor terminal. The resistor terminal voltage is a voltage at the resistor terminal.

Semiconductor devices including design for test capabilities and semiconductor modules and test systems including such devices

A data receiver includes a first buffer circuit and a second buffer circuit. The first buffer circuit varies a resistance of a data path and a resistance of a reference voltage path based on a plurality of control signals, and adjusts a voltage level of an input data signal and a level of a reference voltage to generate an internal data signal and an internal reference voltage based on the varied resistance of the data path and the varied resistance of the reference voltage path. The second buffer circuit compares the internal data signal with the internal reference voltage to generate a data signal.

Data receiver, semiconductor device and memory device including the same

Example embodiments disclose a semiconductor device having an on-die termination (ODT) structure that reduces current consumption, and a termination method performed in the semiconductor device. The semiconductor device includes a calibration circuit for generating calibration codes in response to a reference voltage and a voltage of a calibration terminal connected to an external resistor and an on-die termination device for controlling a termination resistance of a data input/output pad in response to the calibration codes and an on-die termination control signal. The termination resistance of the data input/output pad is greater than a resistance of the calibration terminal.

Semiconductor devices having on-die termination structures for reducing current consumption and termination methods performed in the semiconductor devices

A memory device controller having a write leveling mode of operation comprises: a clock generator that generates a periodic clock signal for transmission to a memory device; a data strobe generator that generates a data strobe signal for transmission to the memory device; and a control unit that generates command signals for transmission to the memory device, the controller, during operation in the write leveling mode, generating a command signal and a write leveling control signal for transmission to the memory device.

Memory devices and systems including write leveling operations and methods of performing write leveling operations in memory devices and systems

A phase interpolator includes a delay difference detector and a phase interpolation driver. The delay difference detector receives a delay code to detect a delay difference. The phase interpolation driver includes two or more driver blocks complementarily operating, and the phase interpolation driver interpolate two input signals in response to the delay difference to provide an interpolated output signal. Each of two or more driver blocks includes a plurality of unit drivers, each input of the unit drivers is commonly connected, and each delay of the two or more driver blocks is varied according to the delay difference.

Phase interpolator and delay locked-loop circuit

A semiconductor device receives a command corresponding to a memory access operation and performs the memory access operation after an additive latency period. The additive latency period begins when the command is received. The semiconductor device comprises a phase controller for controlling a phase of a clock signal and outputting a phase-controlled clock signal, and a controller for generating and outputting a control signal for enabling the phase controller that is disabled, at a predetermined time in the additive latency period.

Semiconductor device having additive latency

A semiconductor memory device that includes a supply voltage pad, a ground voltage pad, and at least two data input/output pads arranged between the supply voltage pad and the ground voltage pad. The semiconductor memory device has a first pull-up driver that is connected to the second data input/output pad located at a first distance from the supply voltage pad, and a first pull-down driver that is connected to the first data input/output pad located at a second distance from the ground voltage pad.

Semiconductor memory device having driver for compensating for parasitic resistance of data input-output pads

The DLL circuit includes a control circuit which controls bias currents of the unit delay circuits according to an externally input column address strobe writing latency (CWL) signal, and/or a DCC control circuit which adjusts steps of a DCC current of the DCC according to the externally input column address strobe writing latency (CWL) signal. The CWL signal may be input by a semiconductor memory device and may be indicative of a column address strobe writing latency of the semiconductor memory device. The semiconductor memory device may be a double data rate (DDR) synchronous DRAM (SDRAM) device.

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Seoul, South Korea

Yang-Ki Kim