United Microelectronics Corp.

Yang-Ju Lu

Yen-Chen Chen

Kuo-Chih Lai

Shih-Min Chou

Yun-Tzu Chang

Nien-Ting Ho

Ching-Yun Chang

Wei-Ming Hsiao

Chi-Mao Hsu

Chia-Chang Hsu

Hsiang-Chieh Yen

Wei-Ning Chen

Kun-Ju Li

Fu-Shou Tsai

Chun-Yao Yang

Yu-Lung Shih

Kuan-Chun Lin

Ji-Min Lin

Yong-Yi Lin

Ching-Yang Chuang

Chin-Fu Lin

Bin-Siang Tsai

Chun-Yuan Wu

Min-Chuan Tsai

Ai-Sen Liu

Chun-Ling Lin

Ko-Wei Lin

Jen-Po Huang

Seng Wah Liau

Xu Yang Shen

Yun Tzu Chang

Fang-Yi Liu

A fabricating method of transistors includes providing a substrate with numerous transistors thereon. Each of the transistors includes a gate structure. A gap is disposed between gate structures adjacent to each other. Later, a protective layer and a first dielectric layer are formed in sequence to cover the substrate and the transistors and to fill in the gap. Next, numerous buffering particles are formed to contact the first dielectric layer. The buffering particles do not contact each other. Subsequently, a second dielectric layer is formed to cover the buffering particles. After that, a first planarization process is performed to remove part of the first dielectric layer, part of the second dielectric layer and buffering particles by taking the protective layer as a stop layer, wherein a removing rate of the second dielectric layer is greater than a removing rate of the buffering particles during the first planarization process.

Fabricating method of transistors without dishing occurred during CMP process

The present invention discloses a metal gate process. A sacrificial nitride layer is introduced during the fabrication of metal gates. The gate height can be well controlled by introducing the sacrificial nitride layer. Further, the particle fall-on problem can be effectively solved.

Method of manufacturing a semiconductor device

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region, a second region, a third region, and a fourth region; forming a tuning layer on the second region; forming a first work function metal layer on the first region and the tuning layer of the second region; forming a second work function metal layer on the first region, the second region, and the fourth region; and forming a top barrier metal (TBM) layer on the first region, the second region, the third region, and the fourth region.

Method for fabricating semiconductor device

Semiconductor device and method for fabricating the same

A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an isolation layer, a gate dielectric layer, a tantalum nitride layer, a tantalum oxynitride layer, an n type work function metal layer and a filling metal. The isolation layer is formed on a substrate, and the isolation layer has a first gate trench. The gate dielectric layer is formed in the first gate trench, the tantalum nitride layer is formed on the gate dielectric layer, and the tantalum oxynitride layer is formed on the tantalum nitride layer. The n type work function metal layer is formed on the tantalum oxynitride layer in the first gate trench, and the filling metal is formed on the n type work function metal layer in the first gate trench.

Semiconductor structure and manufacturing method thereof

A method for fabricating a metal-insulator-metal (MIM) capacitor includes the steps of: forming a capacitor bottom metal (CBM) layer on a material layer; forming a silicon layer on the CBM layer; forming a capacitor dielectric layer on the silicon layer; and forming a capacitor top metal (CTM) layer on the capacitor dielectric layer.

Method for fabricating a MIM capacitor

A method for modulating a work function of a semiconductor device having a metal gate structure including the following steps is provided. A first stacked gate structure and a second stacked gate structure having an identical structure are provided on a substrate. The first stacked gate structure and the second stacked gate structure respectively include a first work function metal layer of a first type. A patterned hard mask layer is formed. The patterned hard mask layer exposes the first work function metal layer of the first stacked gate structure and covers the first work function metal layer of the second stacked gate structure. A first gas treatment is performed to the first work function metal layer of the first stacked gate structure exposed by the patterned hard mask layer. A gas used in the first gas treatment includes nitrogen-containing gas or oxygen-containing gas.

Method for modulating work function of semiconductor device having metal gate structure by gas treatment

A semiconductor structure comprises a first wire level, a second wire level and a via level. The first wire level comprises a first conductive feature. The second wire level is disposed on the first wire level. The second wire level comprises a second conductive feature and a third conductive feature. The via level is disposed between the first wire level and the second wire level. The via level comprises a via connecting the first conductive feature and the second conductive feature. There is a first air gap between the first conductive feature and the second conductive feature. There is a second air gap between the second conductive feature and the third conductive feature. The first air gap and the second air gap are linked.

Semiconductor structure and method for manufacturing the same

The present invention provides a method for metal gate work function tuning before contact formation in a fin-shaped field effect transistor (FinFET), where in the method comprises the following steps. (S) providing a substrate having a metal gate structure on a side of the substrate, (S) forming a titanium nitride (TiN) layer on the side of the substrate, and (S) performing a gate annealing to tune work function of the metal gate structure.

Method for tuning metal gate work function before contact formation in fin-shaped field effect transistor manufacturing process

A metal gate forming process includes the following steps. A first metal layer is formed on a substrate by at least a first step followed by a second step, wherein the processing power of the second step is higher than the processing power of the first step.

Metal gate forming process

Growing community of inventors

Changhua County, Taiwan

Yang-Ju Lu