Alibaba Group Holding Limited

Samsung Electronics Co., Ltd.

Google Inc.

T-head (shanghai) Semiconductor Co., Ltd.

Yang Jiao

Liang Han

Yang Zhang

Zhuo Zhang

Ruoyi Jiang

Dinah Shender

Sen Li

Junji Takagi

Mert Dikmen

Amy Richardson

Xinlong Bao

Mitchell K Alsup

Boris Beylin

YunXiao Zou

Maxim Lukyanov

Jing Wang

Ali Nasiri Amini

Alexander Grosul

Chengyuan Wu

Guoyu Zhu

Rong Zhong

Yijung Su

Long Chen

Yi Jung Su

Methods, systems, and computer programs encoded on a computer storage medium, for training and using machine learning models are disclosed. Methods include creating a model that represents relationships between user attributes, content exposures, and performance levels for a target action using organic exposure data specifying one or more organic exposures experienced by a particular user over a specified time prior to performance of a target action by the particular user and third party exposure data specifying third party exposures of a specified type of digital component to the particular user over the specified time period. Using the model, an incremental performance level attributable to each of the third party exposures at an action time when the target action was performed by the particular user is determined. Transmission criteria for at least some digital components to which the particular user was exposed are modified based on the incremental performance.

Contribution incrementality machine learning models

The presented systems enable efficient and effective network communications. In one embodiment, a system comprises a parallel processing unit (PPU) included in a chip and a plurality of interconnects in an inter-chip network (ICN) configured to communicatively couple a plurality of PPUs that communicate with one another via the ICN. Corresponding communications are configured in accordance with routing tables. The routing tables can be stored and reside in registers of an ICN subsystem included in the PPU and include indications of minimum links available to forward a communication from the PPU and another PPU. Respective ones of the routing tables include indications of a correlation between the minimum links and respective ones of a plurality of egress ports that are available for communication coupling to the respective ones of PPUs that are possible destination PPUs. The routing tables can include indications of a single path between two PPUs per respective information communication flow.

Parallel dataflow routing scheme systems and methods

The present disclosure provides a method for syncing data of a computing task across a plurality of groups of computing nodes, each group comprising a set of computing nodes A-D, a set of intra-group interconnects that communicatively couple computing node A with computing nodes B and C and computing node D with computing nodes B and C, and a set of inter-group interconnects that communicatively couple a computing node A of a first group of the plurality of groups with a computing node A of a second group neighboring the first group, a computing node B of the first group with a computing node B of the second group, a computing node C of the first group with the computing node C of the second group, and a computing node D of the first group with a computing node D of the second group, the method comprising: syncing across a first dimension of computing nodes using a first set of ring connections, wherein the first set of ring connections are formed using inter-group and intra-group interconnects that communicatively couple the computing nodes along the first dimension; and broadcasting synced data across a second dimension of computing nodes using a second ring connection.

Efficient and more advanced implementation of ring-allreduce algorithm for distributed parallel deep learning

Embodiments of the present disclosure present a hyper-square interconnect topology and advanced ring-based AllReduce operations. In some embodiments, a topology is provided that is an improvement over conventional interconnect topologies by eliminating delays associated with long wirings. In some embodiments, computing nodes are divided into sub-sections to better allocate computing tasks, and the system can be optimized to divide up the computing nodes by maximizing the number of square sub-sections in the topology. In some embodiments, the system can be optimized to select square sub-sections first for each computing task. Each sub-section can comprise some computing nodes or all computing nodes in the hyper-square interconnect topology. This flexibility allows the hyper-square interconnect topology to utilize the computing nodes more efficiently by assigning appropriate numbers of computing nodes to each computing task based on the computing need of the computing task.

Efficient inter-chip interconnect topology for distributed parallel deep learning

The present disclosure relates to methods and apparatuses for execution of a neural network. An exemplary method can be implemented by a processing unit. The processing unit can include a command parser configured to dispatch commands and computing tasks and at least one core communicatively coupled with the command parser and configured to process the dispatched computing task. Each core can include a convolution unit, a pooling unit, at least one operation unit and a sequencer communicatively coupled with the convolution unit, the pooling unit, and the at least one operation unit and configured to distribute instructions of the dispatched computing task to the convolution unit, the pooling unit, and the at least one operation unit for execution. The method can include: reading, by the convolution unit, data from a local memory of the at least one operation unit; performing, by the convolution unit, a convolution operation on the data to generate a feature map; and performing, by the pooling unit, a pooling operation on the feature map.

Method and apparatus for execution of neural network

The present disclosure relates to a device for executing a convolutional neural network operation. The device comprises a first memory, a processing array comprising a plurality of processing strings, and a controller. The controller can be configured to fetch one or more batches of data into the first memory, regroup the one or more batches of data into multiple work items, wherein a first work item partially overlaps one or more work items among the multiple work items, and broadcast the multiple work items to the processing array, wherein the first work item is transferred to two or more processing strings of the processing array.

Data reuse and efficient processing scheme in executing convolutional neural network

The present disclosure provides a method for syncing data of a computing task across a plurality of groups of computing nodes. Each group including a set of computing nodes A-D, a set of intra-group interconnects that communicatively couple computing node A with computing nodes B and C and computing node D with computing nodes B and C, and a set of inter-group interconnects that communicatively couple each of computing nodes A-D with corresponding computing nodes A-D in each of a plurality of neighboring groups. The method comprises syncing data at a computing node of the plurality of groups of computing nodes using inter-group interconnects and intra-group interconnects along four different directions relative to the node; and broadcasting synced data from the node to the plurality of groups of computing nodes using inter-group interconnects and intra-group interconnects along four different directions relative to the node.

Hyper-square implementation of tree AllReduce algorithm for distributed parallel deep learning

The present disclosure provides a system comprising: a first group of computing nodes and a second group of computing nodes, wherein the first and second groups are neighboring devices and each of the first and second groups comprising: a set of computing nodes A-D, and a set of intra-group interconnects, wherein the set of intra-group interconnects communicatively couple computing node A with computing nodes B and C and computing node D with computing nodes B and C; and a set of inter-group interconnects, wherein the set of inter-group interconnects communicatively couple computing node A of the first group with computing node A of the second group, computing node B of the first group with computing node B of the second group, computing node C of the first group with computing node C of the second group, and computing node D of the first group with computing node D of the second group.

Efficient and more advanced implementation of ring-AllReduce algorithm for distributed parallel deep learning

Units of shader work, such as warps or wavefronts, are grouped into clusters. An individual vector register file of a processor is operated as segments, where a segment may be independently operated in an active mode or a reduced power data retention mode. The scheduling of the clusters is selected so that a cluster is allocated a segment of the vector register file. Additional sequencing may be performed for a cluster to reach a synchronization point. Individual segments are placed into the reduced power data retention mode during a latency period when the cluster is waiting for execution of a request, such as a sample request.

Warp clustering

A method for computing in a thread-based environment provides manipulating an execution mask to enable and disable threads when executing multiple conditional function clauses for process instructions. Execution lanes are controlled based on execution participation for the process instructions for reducing resource consumption. Execution of particular one or more schedulable structures that include multiple process instructions are skipped based on the execution mask and activating instructions.

Growing community of inventors

San Mateo, CA, United States of America

Yang Jiao