Globalfoundries Singapore Pte. Ltd.

Codexis, Inc.

Intel Corporation

Yang Hong

Tze Ho Simon Chan

Steven James Collier

Derek J Smith

Jeffrey C Moore

Haibin Chen

Fabien Louis Cabirol

Yong Koy Bong

Martina Quintanar-Audelo

Tao Li

Yong Wee Francis Poh

Anupam Gohel Prafulchandra

El Mehdi Boujamaa

Francis YongWee Poh

Martin Ostermayr

Juan Boon Tan

Wanbing Yi

Yi Jiang

Shifeng Zhao

The present disclosure provides engineered proline hydroxylase polypeptides for the production of hydroxylated compounds, polynucleotides encoding the engineered proline hydroxylases, host cells capable of expressing the engineered proline hydroxylases, and methods of using the engineered proline hydroxylases to prepare compounds useful in the production of active pharmaceutical agents.

Biocatalysts and methods for hydroxylation of chemical compounds

Engineered proline hydroxylase polypeptides and methods

Engineered proline hydroxylase polynucleotides and methods

Methods for hydroxylyation of chemical compounds

A memory circuit, comprises a first set of memory cells configured to operate in a direct access mode or in a refresh mode and a second set of memory cells configured to operate in the direct access mode and in the refresh mode. The memory circuit further comprises a controller configured to receive a write request and to execute the write request for a set of memory cells being in direct access mode; and to buffer the write request for later execution for a set of memory cells being in refresh mode.

Memory circuit and method for operating a first MRAM and a second MRAM set of memory cells configured to operate in a direct access mode and/or refresh mode

A memory circuit (), comprises a first set of memory cells () configured to operate in a direct access mode or in a refresh mode and a second set of memory cells () configured to operate in the direct access mode and in the refresh mode. The memory circuit () further comprises a controller () configured to receive a write request and to execute the write request for a set of memory cells being in direct access mode; and to buffer the write request for later execution for a set of memory cells being in refresh mode.

Memory circuit and method for operating a first and a second set of memory cells in direct memory access mode with refresh

The present disclosure provides engineered proline hydroxylase polypeptides for the production of hydroxylated compounds, polynucleotides encoding the engineered proline hydroxylases, host cells capable of expressing the engineered proline hydroxylases, and methods of using the engineered proline hydroxylases to prepare compounds useful in the production of active pharmaceutical agents. The present disclosure provides engineered proline hydroxylase biocatalysts, polynucleotides encoding the biocatalysts, methods of their preparation, and processes for preparing hydroxylated compounds using these engineered biocatalysts.

Engineered proline hydroxylase polypeptides

Memory cell, method for operating the memory cell and method of forming the memory cell are disclosed. The memory cell includes a first selector having a first select transistor with a first gate coupled to a first wordline and first and second source/drain (S/D) regions, and a second selector having at least a second select transistor with a second gate coupled to a second wordline and first and second S/D regions. The memory cell includes a first magnetic tunnel junction (MTJ) element coupled between a first bit line and the first S/D region of the first select transistor, and a second MTJ element coupled between a second bit line and the first S/D region of the second select transistor.

Low power memory cell with high sensing margin

A method of fabricating an integrated circuit includes depositing a bottom electrode layer, an MTJ layer, and a top electrode layer over a passivation layer and within a trench of the passivation layer and removing portions of the MTJ layer and the top electrode layer to form an MTJ/top electrode stack over the bottom electrode layer and at least partially within portions of the trench having being reopened by said removing. The method further includes forming a further passivation layer over the MTJ/top electrode stack, forming a further ILD layer of the further passivation layer, and reforming a top electrode layer over the ILD layer and over the MTJ/top electrode stack. Still further, the method includes removing portions of the bottom electrode layer, the further passivation layer, the further ILD layer, and the re-formed top electrode layer to form a bottom electrode/MTJ/top electrode stack.

Methods for fabricatingintegrated circuits with spin torque transfer magnetic randomaccess memory (STT-MRAM) including a passivation layer formed along lateral sidewalls of a magnetic tunnel junction of the STT-MRAM

A multi-bit NVM cell includes a storage unit having resistive elements, such as phase change resistive elements. The NVM cell may be configured as a single port or dual port multi-bit cell. The NVM cell includes primary and secondary cell selectors. The primary selector selects the multi-bit cell while the secondary selector selects a bit within the multi-bit cell. A plurality of storage units can be commonly coupled to a primary selector, facilitating high density applications.

Resistive non-volatile memory

A multi-bit NVM cell includes a storage unit having resistive elements, such as phase change resistive elements. The NVM cell may be configured as a single port or dual port multi-bit cell. The NVM cell includes a cell selector. The cell selector selects the multi-bit cell. When appropriate signals are applied to the NVM cell, the cell selector selects an appropriate resistive element of the storage unit. A plurality of storage units can be commonly coupled to the cell selector, facilitating high density applications.

Stackable non-volatile memory

Disclosed herein are memory cell arrays, semiconductor devices, and methods for fabricating semiconductor devices. In one embodiment, a memory cell array includes first, second, third, and fourth memory cells each having a first transistor and a second transistor. First and second word-lines are coupled with the gates of the first transistors of the first and second memory cells. The second and a third word-line are coupled with the gates of the second transistors of the third and fourth memory cells.

Non-volatile memory cell arrays and methods of fabricating semiconductor devices

An embodiment, relates to a phase changeable memory cell. The phase changeable memory cell is formed with an ultra small contact area formed by filament conductive path. This contact area between a heating electrode and phase changeable material layer is determined by the forming of filament path, which is conductive and much smaller in cross-sectional area than the minimum area that can be achieved by lithography. This leads to high heating efficiency and ultra-low programming current. As the disclosed structure has no requirement on endurance for the formed filament and use phase changeable material rather than filament-forming material to provide high on/off resistance ratio, drawbacks of filament-forming material on low endurance and low sensing margin are avoided in the proposed cell structure. Therefore, by using ReRAM-related filament-forming materials to get sub-litho-dimension conductive path as heating electrode and using high on/off ratio phase changeable material as the storage media, it is possible to reduce the power consumption of phase changeable memory dramatically without the drawbacks of filament-forming materials that are shown in ReRAM.

Nonvolative memory with filament

A phase changeable memory cell is disclosed. In an embodiment of the invention, a phase changeable memory cell is formed with an ultra-small contact area to reduce the programming current. This contact area between heater electrode and phase changeable material is limited by the thickness of thin films rather than lithographic critical dimension in one dimension. As a result, the contact area is much less than the square of lithographic critical dimension for almost every technology node, which is helps in reducing current. To further reduce the current and improve the heating efficiency, heater electrode is horizontally put with its length being tunable so as to minimize the heat loss flowing through the heater to the terminal that connects to the front end switch device. In addition, above and below the heater layer, low-thermal-conductivity material (LTCM) is used to minimize heat dissipation. This results in reduced power consumption of the phase changeable memory cell with improved reliability.

Growing community of inventors

Singapore, Singapore

Yang Hong