Freescale Semiconductor,inc.

Motorola Corporation

University of Texas System

Yang Du

Leo Mathew

Voon-Yew Thean

Bich-Yen Nguyen

Gary T Rochelle

Ertugrul Demircan

Surya Veeraraghavan

Alain C Duvallet

Rainer Thoma

Thu Nguyen

Glenn O Workman

Omkar Namjoshi

Le Li

Suman Kumar Banerjee

Compositions and methods related to the removal of acidic gas. In particular, the present disclosure relates to a composition and method for the removal of acidic gas from a gas mixture using a solvent comprising a blend of piperazine and at least one diamine or triamine.

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A method of forming a semiconductor device is provided in which a substrate () is provided which has a gate dielectric layer () disposed thereon, and a gate electrode () having first and second sidewalls is formed over the gate dielectric layer. First () and second () extension spacer structures are formed adjacent the first and second sidewalls, respectively. In the resulting device: (a) the first and second extension spacer structures have different dimensions; (b) the first and second extension spacer structures comprise first and second distinct materials; (c) the device has asymmetric source/drain extensions (); and/or (d) the device has an oxide layer () disposed between the first extension spacer structure and the gate electrode, and either (i) the device has no dielectric layer disposed between the second extension spacer structure and the gate electrode, or (ii) the device has a second dielectric layer disposed between the second extension spacer structure and the gate electrode, and the first dielectric layer is substantially thicker than the second dielectric layer.

Asymmetric spacers and asymmetric source/drain extension layers

A semiconductor optical device includes an insulating layer, a photoelectric region formed on the insulating layer, a first electrode having a first conductivity type formed on the insulating layer and contacting a first side of the photoelectric region, and a second electrode having a second conductivity type formed on the insulating layer and contacting a second side of the photoelectric region. The photoelectric region may include nanoclusters or porous silicon such that the device operates as a light emitting device. Alternatively, the photoelectric region may include an intrinsic semiconductor material such that the device operates as a light sensing device. The semiconductor optical device may be further characterized as a vertical optical device. In one embodiment, different types of optical devices, including light emitting and light sensing devices, may be integrated together. The optical devices may also be integrated with other types of semiconductor devices, such as vertical field-effect transistors.

Semiconductor optical devices having fin structures

Semiconductor optical devices and method for forming

A double gate semiconductor device () is used beneficially as a multiplier (). The double gate semiconductor device () has a lateral fin () as the channel region with the gates formed opposite each other on both sides of the fin. The lateral positioning of the fin provides symmetry between the two gates. To increase drive current, multiple transistors are easily connected in parallel by having a continuous fin structure () with alternating source/drain terminals () in which the sources are connected together and the drains are connected together. Gates () are positioned between each pair of adjacent source/drain terminals and electrically connected together. The multiplier () may also be used as a mixer and further as a phase detector.

Method and circuit for multiplying signals with a transistor having more than one independent gate structure

A method for forming a silicon-on-insulator transistor () includes forming an active region () overlying an insulating layer (), wherein a portion of the active region provides an intrinsic body region (). A body tie access region () is also formed within the active region, overlying the insulating layer and laterally disposed adjacent the intrinsic body region, making electrical contact to the intrinsic body region. A gate electrode () is formed overlying the intrinsic body region for providing electrical control of the intrinsic body region, the gate electrode extending over a portion () of the body tie access region. The gate electrode is formed having a substantially constant gate length () along its entire width overlying the intrinsic body region and the body tie access region to minimize parasitic capacitance and gate electrode leakage. First and second current electrodes () are formed adjacent opposite sides of the intrinsic body region. In addition, a body tie diffusion () is formed within the active region and laterally offset from the body tie access region and electrically coupled to the body tie access region.

Method and apparatus for forming an SOI body-contacted transistor

An integrated circuit capacitor ( ) uses multiple electrically conductive stacks ( ) to optimize capacitance density. A second stack ( ) is a first nearest neighbor to a first stack ( ). A third stack ( ) is a second nearest neighbor to the first stack. Each of the three stacks defines vertices of an isosceles triangle ( ) formed in a plane substantially perpendicular to the three stacks. The isosceles triangle does not have a ninety degree angle. The isosceles triangle may also be implemented as an equilateral triangle.

Integrated vertical stack capacitor

A semiconductor device ( ) includes an isolated p-well ( ) formed in a substrate ( ) by a buried n-well ( ) and an n-well ring ( ). The n-well ring ( ) extends from a surface of the semiconductor device ( ) to the buried n-well ( ). The isolated p-well ( ) includes a plurality of n-well plugs ( ) extending from the surface of the semiconductor device ( ) into the isolated p-well ( ) and contacting the buried n-well ( ). The plurality of n-well plugs ( ) reduces an n-well resistance to provide better noise isolation for high frequency signals.

Growing community of inventors

Austin, TX, United States of America

Yang Du