Taiwan Semiconductor Manufacturing Comp. Ltd.

National Applied Research Laboratories

Yang-Chih Hsueh

Wen-Chih Chiou

Chia-Yin Chen

Yan-Zuo Tsai

Tsang-Jiuh Wu

Yung-Chi Lin

Ebin Liao

Fu-Kang Tien

Tsong-Pyng Perng

Hsiao Yun Lo

Chien-Nan Hsiao

Chi-Chung Kei

Chien-Pao Lin

Bo-Heng Liu

I-Chun Hsu

Provided are a semiconductor device and a method for manufacturing the same, and a semiconductor package. The semiconductor device includes a die stack and a cap substrate. The die stack includes a first die, second dies stacked on the first die, and a third die stacked on the second dies. The first die includes first through semiconductor vias. Each of the second dies include second through semiconductor vias. The third die includes third through semiconductor vias. The cap substrate is disposed on the third die of the die stack. A sum of a thickness of the third die and a thickness of the cap substrate ranges from about 50 μm to about 80 μm.

Semiconductor device and method for manufacturing the same, and semiconductor package

A method and apparatus for bonding semiconductor devices are disclosed. In an embodiment, the method may include attaching a first die to a flip head of a flip module, flipping the first die with the flip module, removing the first die from the flip module after flipping the first die, inspecting the flip head of the flip module for contamination after removing the first die, cleaning the flip head with an in situ cleaning module after inspecting the flip head, and attaching a second die to the flip head after cleaning the flip head.

Method and apparatus for bonding semiconductor devices

An interconnection structure and method disclosed for providing an interconnection structure that includes conductive features having reduced topographic variations. The interconnection structure includes a contact pad disposed over a substrate. The contact pad includes a first layer of a first conductive material and a second layer of a second conductive material over the first layer. The first conductive material and the second conductive material are made of substantially the same material and have a first average grain size and a second average grain size that is smaller than the first average grain size. The interconnection structure also includes a passivation layer covering the substrate and the contact pad, and the passivation layer has an opening exposing the contact pad.

Interconnection structure with confinement layer

The present invention provides methods and designs of enclosed-channel reactor system for manufacturing catalysts or supports. Both of the configuration designs force the gaseous precursors and purge gas flow through the channel surface of reactor. The precursors will transform to thin film or particle catalysts or supports under adequate reaction temperature, working pressure and gas concentration. The reactor body is either sealed or enclosed for isolation from atmosphere. Another method using super ALD cycles is also proposed to grow alloy catalysts or supports with controllable concentration. The catalysts prepared by the method and system in the present invention are noble metals, such as platinum, palladium, rhodium, ruthenium, iridium and osmium, or transition metals such as iron, silver, cobalt, nickel and tin, while supports are silicon oxide, aluminum oxide, zirconium oxide, cerium oxide or magnesium oxide, or refractory metals, which can be chromium, molybdenum, tungsten or tantalum.

Enclosed-channel reactor method to manufacture catalysts or support materials

Enclosed-channel reactor system and method to manufacture catalysts or support

Growing community of inventors

Hsinchu, Taiwan

Yang-Chih Hsueh