Cisco Technology, Inc.

Black Sesame Technologies Inc.

Yanfeng Wang

Sharat C Prasad

Yu Deng

Sriram Natarajan

Zheng Qi

Yi Wang

Terry Seaver

Luis M Hernandez

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for controlling, by an on-chip memory controller, a plurality of hardware components that are configured to perform computations to access a shared memory. One of the on-chip memory controller includes at least one backside arbitration controller communicatively coupled with a memory bank group and a first hardware component, wherein the at least one backside arbitration controller is configured to perform bus arbitrations to determine whether the first hardware component can access the memory bank group using a first memory access protocol; and a frontside arbitration controller communicatively coupled with the memory bank group and a second hardware component, wherein the frontside arbitration controller is configured to perform bus arbitrations to determine whether the second hardware component can access the memory bank group using a second memory access protocol different from the first memory access protocol.

High-performance on-chip memory controller

The link status of a Fibre-Channel link interconnecting two Fibre-Channel ports may be determined by a third entity distinct from the two Fibre-Channel ports. The third entity may be a transport interface used to connect one of the Fibre-Channel ports to a transport network that carries the link. The transport interface may also learn the Fibre-Channel port types of the two ports.

Apparatus and method for enabling intelligent Fibre-Channel connectivity over transport

Supplemental flow control mechanisms are provided to facilitate efficient data exchange between Fibre Channel ports over extended distances. In one implementation, a supplemental buffer mechanism is maintained and managed in part by substituting a locally generated ready indication signal for the remotely generated ready indication signal provided by the Fibre Channel standard. In this way, data flow may be adjusted optimally irrespective of the relatively long propagation time of the ready signals exchanged by the two sides of the link.

Intelligent flow control management to extend fibre channel link full performance range

A packet switching system and method are disclosed. The system includes a plurality of input and output ports and an input buffer at each of the input ports. The system further includes an input scheduler associated with each of the input buffers and a centralized memory shared by the output ports. An output buffer is located at each of the output ports and an output scheduler is associated with each of the output ports. Each of the input buffers comprises a plurality of virtual output queues configured to store a plurality of packets in a packed arrangement.

Centralized memory based packet switching system and method

The Fibre-Channel flow control mechanism is augmented to facilitate efficient data exchange between Fibre-Channel ports over extended distances. A supplemental buffer mechanism may be maintained as part of an interface to a transport network used to carry Fibre-Channel traffic. The transport network interface makes a remote Fibre-Channel port aware of the augmented local receiver buffer capacity by intercepting certain frames used in link establishment and substituting an enhanced buffer capacity for the local Fibre-Channel port's internal buffer capacity. This technique provides improved throughput and readily accommodates large distances and large frame sizes.

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Fremont, CA, United States of America

Yanfeng Wang