Fujitsu Corporation

Fujitsu Semiconductor Limited

Yanfei Chen

Sanroku Tsukamoto

Hirotaka Tamura

Masato Yoshioka

Tatsuya Ide

A Boltzmann machine circuit includes: a plurality of circuits each circuit configured to add one or more first values based on one or more outputs of one or more circuits which are included in the plurality of circuits and are other than the circuit and convert an addition result into an analog signal, compare the analog signal with a second value, and output a comparison result; a plurality of arithmetic circuits configured to multiply the respective comparison results by respective weight values and generate the first values; and a control circuit configured to amplify an amplitude of the analog signal generated by each of the plurality of circuits.

Boltzmann machine circuit

A comparator includes an input-stage circuit that sets, in a first operating state, two voltage signals in a first voltage state, and changes, in a second operating state, the two voltage signals from the first voltage state to a second voltage state at different speeds, a latch-stage circuit that includes two field effect transistors and two inverters, the two field effect transistors receiving the two voltage signals at control nodes and disposed between two output nodes and a predetermined potential, the two inverters cross-coupled between the two output nodes and placed in an inactive state in the first operating state and in an active state in the second operating state, and a control circuit that controls current capacities in two paths through which drive voltages are applied to the two inverters, causing the current capacities to be different during at least part of a period of the second operating state.

Comparator with controlled current supply capacity

A method for detecting a hysteresis characteristic of a comparator, include: causing a controller to control an offset adjuster configured to adjust an offset amount of the comparator; causing the controller to change the offset amount from a first value toward a second value and detect a third value when a logic level of a signal output from the comparator is changed; causing the controller to change the offset amount from the second value toward the first value and detect a fourth value when the logic level is changed; and causing the controller to detect the hysteresis characteristic of the comparator based on a first difference between the third value and the fourth value.

Method for detecting hysteresis characteristic of comparator and semiconductor device

A charge transfer circuit has a charge transfer unit including an input charge holding element holding an input charge, an output charge holding element holding an output charge, and a charge transfer element, provided between a first node of the input charge holding element and a second, node of the output charge holding element, to transfer the charge held by the input charge holding element to the output charge holding element, an error sensing circuit detecting a third voltage corresponding to a first voltage of the first node when the charge transfer element finished transferring the charge from the input charge holding element to the output charge holding element, and an error correction unit correcting a second voltage of the second node when the charge transfer finished based on the third voltage and eliminate an error included in the second voltage of the second node.

Charge transfer circuit

A CDR circuit includes an AD converter that converts an analog input signal to a digital output signal according to an operation clock signal; a phase adjuster that subtracts a first phase from a first clock signal having a first frequency equal to a frequency of the input signal to output a second clock signal having a second frequency as the operation clock signal to the AD converter; a phase detector that detects a second phase in the output signal of the AD converter; a filter that obtains a third phase by performing a filtering process based on the first phase, the second phase, and the third phase output from the filter; an adder that adds the first phase and the third phase to obtain a fourth phase; and a decision circuit that obtains recovered data from the output signal of the AD converter using the fourth phase.

Clock and data recovery circuit

An analog/digital converter includes: a first analog/digital conversion unit that performs digital conversion on received first analog input voltage in a first time period; a second analog/digital conversion unit that performs digital conversion on received second analog input voltage in a second time period that is different from the first time period; and a first coupling capacitor that connects the first analog/digital conversion unit and the second analog/digital conversion unit, and wherein the second analog/digital conversion unit receives, through the first coupling capacitor, first residual voltage that is remaining voltage of the first analog input voltage on which digital conversion is performed in the first analog/digital conversion unit, as the second analog input voltage.

Analog/digital converter

An analog-digital converter apparatus includes a plurality of AD converters connected in series, each AD converter to convert an analog signal received by a first AD converter, at least one of the AD converters including: a residual signal generator that generates a first residual signal, the first residual signal being a difference between the analog signal or one of two residual signals amplified and output by a preceding AD converter and a first reference signal, and a second residual signal, the second residual signal being a difference between the analog signal or one of the two residual signals and a second reference signal; and an amplifier that amplifies and outputs the first residual signal to a subsequent AD converter at a first timing and amplifies and outputs the second residual signal to the subsequent AD converter at a second timing.

AD converter apparatus, AD converter circuit, and AD conversion method

A low-power and high-speed ADC includes: a successive approximation converter circuit configured to sequentially compare and coarsely convert the analog input signal voltage into a digital signal with a number of higher-order bits, and also to output a residual voltage; a fixed-quantity change time measurement converter circuit configured to finely convert the residual voltage into a digital signal with a number n of lower-order bits by changing the residual voltage at a fixed rate of change and by measuring the time until a predetermined value is reached; and an encoder circuit configured to generate a digital signal with the predetermined number of bits by combining the digital signal with the number of higher-order bits output from the successive approximation converter circuit and the digital signal with the number of lower-order bits output from the fixed-quantity change time measurement converter circuit.

AD converter circuit and ad conversion method

An analog-to-digital converter includes a digital-to-analog (DA) converting part having a predetermined number of gradation converting stages and configured to cause each of the predetermined number of gradation converting stages to convert a digital signal to an analog signal and output the converted analog signal, a main-comparator configured to output a binary signal on the basis of a first comparison result between the analog signal output from the DA converting part and a predetermined reference level, and a second sub-comparator having an offset less than a quantization unit with respect to the main-comparator and being configured to output a binary signal on the basis of a second comparison result between the analog signal output from the DA converting part and the predetermined reference level.

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Yokohama, Japan

Yanfei Chen