Qualcomm Incorporated

Yandong Gao

Xia Li

Zhongze Wang

Ye Lu

Xiaochun Zhu

Xiaonan Chen

Sunil Sharma

Channappa Desai

Anne Srikanth

Pradeep Jayadev Kodlipet

Chulmin Jung

Changho Jung

Mustafa Badaroglu

Venugopal Boynapalli

Arun Babu Pallerla

Sung Son

Kalyan Kumar Oruganti

Diwakar Singh

Sreeram Gurram

Venkata Balakrishna Reddy Thumu

Jason Cheng

Digital compute-in-memory (DCIM) bit cell circuit layouts and DCIM array circuits for multiple operations per column are disclosed. A DCIM bit cell array circuit including DCIM bit cell circuits comprising exemplary DCIM bit cell circuit layouts disposed in columns is configured to evaluate the results of multiple multiply operations per clock cycle. The DCIM bit cell circuits in the DCIM bit cell circuit layouts each couples to one of a plurality of column output lines in a column. In this regard, in each cycle of a system clock, each of the plurality of column output lines receives a result of a multiply operation of a DCIM bit cell circuit coupled to the column output line. The DCIM bit cell array circuit includes digital sense amplifiers coupled to each of the plurality of column output lines to reliably evaluate a result of a plurality of multiply operations per cycle.

Digital compute-in-memory (DCIM) bit cell circuit layouts and DCIM arrays for multiple operations per column

Certain aspects provide a circuit for in-memory computation. The circuit generally includes an in-memory computation array having a plurality of computation circuits, each of the computation circuits being configured to perform a dot product computation. In certain aspects, each of the computation circuits includes a memory cell, a capacitive element, a precharge transistor coupled between an output of the memory cell and the capacitive element, and a read transistor coupled between a read bit line (RBL) and the capacitive element.

Memory cell for dot product operation in compute-in-memory chip

An SRAM array circuit in which a horizontal N-well of a well tap cell in a first row separated from a horizontal N-well of a well tap cell in a second row by a P-type substrate region is disclosed. The well tap cells include a bilateral P-type well tap disposed in the P-type substrate region between the horizontal N-wells in the first and second rows providing ground voltage to the P-type substrate on both sides of a column of well tap cells in the SRAM array circuit, rather than one P-type well tap for each side. Well tap cells without a vertical N-well reduces width, which corresponds to a reduction in width of the SRAM array circuit. The bilateral P-type well tap in a P-type implant region may include a plurality of folded fingers providing the ground voltage to the P-type substrate.

Static random-access memory (SRAM) array circuits including bilateral well tap cells with reduced width folded finger structure

An IC includes a first memory block, a second memory block, and a first memory border cell between the first memory block and the second memory block. The first memory border cell includes a first memory core endcap to the first memory block on a first side of the cell. The first memory border cell further includes a second memory core endcap to the second memory block on a second side of the cell. The second side is opposite the first side. The first memory border cell further includes a memory gap portion between the first memory core endcap and the second memory core endcap. The memory gap portion provides a gap between the first memory core endcap and the second memory core endcap.

Memory

A bitcell architecture for a pseudo-triple-port memory is provided that includes a a bitcell arranged on a semiconductor substrate, the bitcell defining a bitcell width and a bitcell height and including a first access transistor and a second access transistor. A first metal layer adjacent the semiconductor substrate is patterned to form a pair of local bit lines arranged within the bitcell width. The pair of local bit lines includes a local bit line coupled to a terminal of the first access transistor and includes a complement local bit line coupled to a terminal of the second access transistor.

Pseudo-triple-port SRAM bitcell architecture

A charge sharing Compute In Memory (CIM) may comprise an XNOR bit cell with an internal capacitor between the XNOR output node and a system voltage. Alternatively, a charge sharing CIM may comprise an XNOR bit cell with an internal capacitor between the XNOR output node and a read bit line. Alternatively, a charge sharing CIM may comprise an XNOR bit cell with an internal cap between XNOR and read bit line with a separate write bit line and write bit line bar.

Compute-in-memory bit cell

A memory circuit that includes a memory bitcell. The memory bitcell includes a six-transistor circuit configuration, a first transistor coupled to the six-transistor circuit configuration, a second transistor coupled to the first transistor, a third transistor coupled to the second transistor, and a capacitor coupled to the second transistor and the third transistor. The memory circuit includes a read word line coupled to the third transistor, a read bit line coupled to the third transistor, and an activation line coupled to the second transistor. The memory bitcell may be configured to operate as a NAND memory bitcell. The memory bitcell may be configured to operate as a NOR memory bitcell.

Integrated device comprising memory bitcells comprising shared preload line and shared activation line

Transpose static random access memory (SRAM) bit cells configured for horizontal and vertical read operations are disclosed. In one aspect, a transpose SRAM bit cell includes cross-coupled inverters and horizontal and vertical read access transistors. A word line in first metal layer having an axis in a first direction is electrically coupled to a gate node of the horizontal read access transistor, and a bit line in second metal layer having an axis disposed in a second direction substantially orthogonal to the first direction is electrically coupled to the horizontal read access transistor. A transpose word line in third metal layer having an axis disposed in the second direction is electrically coupled to a gate node of the vertical read access transistor, and a transpose bit line in fourth metal layer having an axis disposed in the first direction is electrically coupled to the vertical read access transistor.

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San Diego, CA, United States of America

Yandong Gao