Integrated Device Technology, Inc.

YanBo Wang

Yue Yu

Craig DeSimone

Praveen Rajan Singh

Alejandro F Gonzalez

Al Xuefeng Fang

A method for responding to a command sequence includes receiving a signal from a host carrying a plurality of commands in the command sequence, detecting a non-consecutive clock associated with a start of a current command in the command sequence, and generating a control signal in an active state to indicate detection of the non-consecutive clock.

Command sequence response in a memory data buffer

A method for responding to a command sequence includes receiving the command sequence associated with a targeted access to a memory system, detecting a non-consecutive clock associated with a start of the command sequence, and generating a control signal in an active state to indicate detection of the non-consecutive clock associated with the start of the command sequence.

An apparatus comprises a plurality of driver circuits and a control registers block. The plurality of driver circuits may be configured to drive a read line in response to a memory signal and a reference voltage. The control registers block generally configures the plurality of driver circuits to implement an asymmetric voltage swing of the read line about a voltage level that is half of the reference voltage.

Asymmetric on-state resistance driver optimized for multi-drop DDR4

An apparatus includes an interface and a circuit. The interface may be configured to generate a read signal that carries read data from a memory channel. The circuit may be configured to (i) modify the read signal with a de-emphasis on each pull up of the read signal and a pre-emphasis on each pull down of the read signal and (ii) transfer the read signal as modified to a memory controller.

Asymmetrical emphasis in a memory data bus driver

An apparatus includes a detector circuit and a data buffer. The detector circuit may be configured to (i) identify a start of a command sequence associated with a directed access to a memory system and (ii) generate a control signal indicating a non-consecutive clock associated with the start of the command sequence. The data buffer circuit may be configured to initialize a condition of a receiver circuit in response to the control signal prior to reception of a first data bit associated with the command sequence.

Inferring sampled data in decision feedback equalizer at restart of forwarded clock in memory system

An apparatus comprising a plurality of driver circuits and a plurality of control registers. The plurality of driver circuits may be configured to modify a memory signal that transfers read data across a read line to a memory controller. The plurality of control registers may be configured to enable one or more of the driver circuits. A pull up strength and a pull down strength of the memory signal may be configured in response to how many of the plurality of driver circuits are enabled. The plurality of driver circuits implement an asymmetric pull up and pull down of the memory signal.

An apparatus includes an interface and a circuit. The interface may be configured to generate a memory signal that carries read data from a memory channel. The circuit may be configured to modify a read signal that transfers the read data across a read line to a memory controller. A filter may delay the memory signal to generate a delayed signal. A driver generally amplifies the memory signal to generate the read signal. The driver may modify the read signal with a de-emphasis on each pull up of the memory signal and a pre-emphasis on each pull down of the memory signal based on the delayed signal.

An apparatus includes a first circuit and a second circuit. The first circuit may be configured to (a) buffer write signals presented on a data bus connected between a memory channel and a memory controller, (b) buffer read signals presented on the data bus and (c) condition the write signals. The conditioning may be implemented by (i) converting the write signals to a first differential write signal on a first differential write line and a second differential write signal on a second differential write line and (ii) connecting (a) a negative impedance and (b) a combined resistive and capacitive load between the first and second differential write lines. The second circuit may be configured to (a) convert the first and the second differential write signals to a single-ended write signal and (b) present the single-ended write signal to the data bus.

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Duluth, GA, United States of America

YanBo Wang