Integrated Device Technology, Inc.

Synaptics Corporation

Nio (anhui) Holding Co., Ltd.

Yanbo Wang

Xiaoqian Zhang

Shubing Zhai

Feng Wang

Hongquan Wang

Xuexin Ding

Xinqing Chen

Yao Xiao

Ye Yuan

Jieying Zhang

ChangXi Xu

Zhuanyao Gu

The application provides a vehicle thermal management system, a vehicle thermal management method and a vehicle. The system includes: a flow path switching valve; a compressor, an in-cabin thermal management flow path; an out-cabin thermal management flow path; and at least one battery module thermal management flow path. A flow path switching valve of the system is used for switching the on/off and flow direction of an intake port of the compressor, an exhaust port of the compressor, the in-cabin thermal management flow path, the out-cabin thermal management flow path, and the battery module thermal management flow path.

Vehicle thermal management system, vehicle thermal management method and vehicle

Methods and systems for peak detection as part of automatic gain control in high-speed communications are provided. A peak detection system uses a portion of an input signal to generate a reference signal for comparison with the input signal. The comparison produces a differential error signal that is in turn used to produce one or more full swing pulses based on the comparison. A pulse counter counts the pulses, and if the count in a single clock cycle is above a determined threshold, a binary error signal is set to indicate a need for correction.

Systems and methods for peak detection in automatic gain control circuits in high-speed wireline communications

The present disclosure provides techniques for recovering source stream clock data at the sink in a high definition multimedia digital content transport system. The disclosure includes a fractional-N Phase-Locked Loop (PLL) based clock generator, a programmable Sigma-Delta Modulator (SDM), and a clock data calibrator to fully recover the original source stream clock data. The fractional-N PLL provides flexible source stream clock recovery. When there is a frequency deviation between the original clock and the regenerated clock, the clock data calibrator control circuit adjusts the clock data, preventing any stream data buffer overflow or underflow problems. The disclosed techniques are compatible with the sink devices based on the standards of DisplayPort and HDMI.

Stream clock recovery in high definition multimedia digital system

A method of calibrating a PLL that includes forcing a control voltage input to a voltage controlled oscillator to be a reference voltage and setting a calibration divider coupled to receive an output clock signal from the voltage controlled oscillator such that the calibration divider utilizes one of a plurality of divisors that results in the output clock signal having a high frequency can substantially avoid overshoot and glitch problems associated with conventional PLL calibrations.

Phase-locked loop

The methods and systems presented herein provide an improved means of correcting the variation of Voltage Output Differential (VOD) in differential drivers. In some embodiments, a high-precision reference voltage is generated not only based on a desired VOD, but also by monitoring the Voltage Common Mode (VCM) in a differential driver. In some embodiments, the VOD is then compared with the high-precision reference voltage to correct the output current. The result is a low-variation output voltage.

Low variation voltage output differential for differential drivers

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Shanghai, China

Yanbo Wang