Arm Limited

Cadence Design Systems, Inc.

Yanbin Jiang

Yew Keong Chong

Cyrus Soli Bamji

Andy Wangkun Chen

Gus Wai-Yan Yeung

Marlin Wayne Frederick, Jr

Sriram Thyagarajan

Brian Tracy Cline

Xiaoqing Xu

Paul Christopher De Dood

Daniel J Albers

Ilhami Torunoglu

Tom Shore

Thanusree Achuthan

Jerry Chaoyuan Wang

David William Granda

Sylvia Xiuhui Li

Brian Douglas Ngai Lee

Emmanuel Jean Marie Olivier Pacaud

Matthieu Domonique Henri Pauly

A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell. Such an approach enables both the schematic and layout to be co-optimized during generation of the layout of the cell.

Computer implemented system and method for generating a layout of a cell defining a circuit component

A method and system are disclosed to optimize an integrated circuit layout design by determining possible lengths of layout rows that will reduce the total area of the integrated circuit layout (FIG.B). The possible row lengths (B) are determined and stored in a memory unit as a set of possible optimal row length values. A set of possible optimal row heights corresponding to the determined set of possible rowlengths is determined and the total chip area is iteratively calculated. Optimal values of rowlength and row height are chosen based upon the maximum chip area reduction. Once the optimal row length and height parameters are chosen, transistor devices placed in each row of the integrated circuit layout are folded to achieve the optimal row length and height.

Method and apparatus to optimize an integrated circuit design using transistor folding

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Fremont, CA, United States of America

Yanbin Jiang