International Business Machines Corporation

Yanai Danan

Xin Zhao

Robert J Allen

Vasant B Rao

Jeffrey Paul Soreff

Yair Fried

Avraham Ayzenfeld

Yossi Shapira

Amir Turi

Amit Shay

Gilad Merran

Oren Ben Gigi

Omri Rafaeli

In an approach to processor dependency-aware instruction execution, responsive to a new instruction being issued to an instruction issue queue in a processor, a future dependency count is incremented for each instruction of a plurality of instructions in the instruction issue queue that has a dependency on the new instruction. The plurality of instructions in the instruction issue queue are prioritized based on the future dependency count. The highest priority instruction of the plurality of instructions in the instruction issue queue is issued.

Processor dependency-aware instruction execution

A method of performing transistor simulation with improved sensitivity to parasitic by model order reduction in transistor-level timing is disclosed. The method includes reducing a number of derivative calculations during transistor simulation by representing parasitics as a reduced-order model, wherein the reducing includes: compressing the parasitics to a reduced-order model; simulating with load which is replaced with the reduced-order model; differentiating results of the simulation with respect to reduced-order model parameters; differentiating parameters of the reduced-order model with respect to parasitic values; differentiating the parasitic values with respect to statistical parameters; and computing the differential results of the simulation with respect to the statistical parameters via chain ruling.

Model order reduction in transistor level timing

Examples of techniques for analyzing and generating timing reports for circuits are described herein. A computer-implemented method includes splitting a netlist or cross section of a circuit into sub-circuits. The method further includes building a timing graph by combining generated timing models of the sub-circuits. The method includes determining a full set of dependencies based on each sub-circuit's dependent configuration parameters. The method also further includes generating a sample plan for each sub-circuit. The method includes receiving results from a simulation for each sub-circuit based on the sample plan for each sub-circuit. The method includes generating algebraic forms for an early delay, a late delay, and a slew by curve fitting across the configuration parameters. The method includes propagating arrival times and slew in algebraic forms throughout the timing graph. The method includes evaluating checks based on selected projections from the timing graph to find a worst slack configuration.

Timing analysis of circuits using sub-circuit timing models

Growing community of inventors

Tel Aviv, Israel

Yanai Danan